MOS Gate Oxide Defects Related to Treatment of Silicon Nitride Coated Wafers Prior to Local Oxidation

1982 ◽  
Vol 129 (5) ◽  
pp. 1066-1070 ◽  
Author(s):  
C. A. Goodwin ◽  
J. W. Brossman
Keyword(s):  
Silicon Nitride ◽  
Gate Oxide ◽  
Local Oxidation ◽  
Oxide Defects ◽  
Mos Gate

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

Optimization of Polysilicon Encapsulated Local Oxidation of Silicon: Cavity Dimension Effects on Mechanical Stress and Gate Oxide Integrity

1998 ◽  
Vol 145 (5) ◽  
pp. 1653-1659 ◽  
Author(s):  
Gonçal Badenes ◽  
Rita Rooyackers ◽  
Stephen K. Jones ◽  
Dave Bazley ◽  
Richard Beanland ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Gate Oxide ◽  
Local Oxidation ◽  
Gate Oxide Integrity

Reliability of 4H-SiC(000-1) MOS Gate Oxide Using N2O Nitridation

2009 ◽  
Vol 615-617 ◽  
pp. 557-560 ◽  
Author(s):  
Takuma Suzuki ◽  
Junji Senzaki ◽  
Tetsuo Hatakeyama ◽  
Kenji Fukuda ◽  
Takashi Shinohe ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Band Offset ◽  
Mos Capacitors ◽  
Conduction Band Offset ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Mos Gate

The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

Effect of Growth Conditions on the Reliability of Ultrathin MOS Gate Oxides

1996 ◽  
Vol 428 ◽  
Author(s):  
Tien-Chun Yang ◽  
Krishna C. Saraswat
Keyword(s):  
Gate Oxide ◽  
Interface State ◽  
Growth Conditions ◽  
Physical Stress ◽  
Constant Current ◽  
Strong Function ◽  
Oxidation Rates ◽  
Mos Devices ◽  
State Generation ◽  
Mos Gate

AbstractIn this work we demonstrate that in MOS devices the reliability of ultrathin (< 100Å) gate oxide is a strong function of growth conditions, such as, temperature and the growth rate. In addition, for constant current gate injection the degradation of SiO2 is enhanced as the thickness is reduced. We attribute this to physical stress in SiO2 resulting from the growth process. The degradation is always more for those growth conditions which result in higher physical stress in SiO2. Higher temperatures and slower oxidation rates allow stress relaxation through viscous flow and hence result in SiO2 of better reliability. We also found that for constant current stressing, the interface damage is more at the collecting electrode than at the injecting electrode. ΔDit (stress induced interface state generation) can be reduced after a high temperature Ar post anneal after the gate oxide growth.

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