A Dynamic Study for Wafer-Level Bonding Strength Uniformity in Low-Temperature Wafer Bonding

2005 ◽  
Vol 8 (10) ◽  
pp. G268 ◽  
Author(s):  
Xuanxiong Zhang ◽  
Jean-Pierre Raskin
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Strength ◽  
Dynamic Study ◽  
Wafer Level ◽  
Strength Uniformity

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000836-000858 ◽  
Author(s):  
Sang Hwui Lee ◽  
Michael Khbeis
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Yield ◽  
Activation Process ◽  
Wafer Level ◽  
3D Integration ◽  
Release Process ◽  
Adhesive Film ◽  
Die Set ◽  
Commercial Off The Shelf

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

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