scholarly journals Photonic Integration on the Hybrid Silicon Evanescent Device Platform

2008 ◽  
Vol 2008 ◽  
pp. 1-17 ◽  
Author(s):  
Hyundai Park ◽  
Alexander W. Fang ◽  
Di Liang ◽  
Ying-Hao Kuo ◽  
Hsu-Hao Chang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Wafer Bonding ◽  
Optical Gain ◽  
Hybrid Structure ◽  
Bonding Process ◽  
Wafer Level ◽  
Device Structure ◽  
Silicon Waveguides ◽  
Hybrid Silicon

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

2005 ◽  
Vol 863 ◽  
Author(s):  
F. Niklaus ◽  
R.J. Kumar ◽  
J.J. McMahon ◽  
J. Yu ◽  
T. Matthias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Layer Thickness ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Bonding Process ◽  
Alignment Accuracy ◽  
Wafer Level ◽  
Bonding Parameters ◽  
Wafer Pair ◽  
The Impact

AbstractWafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing

2016 ◽  
Vol 75 (9) ◽  
pp. 345-353 ◽  
Author(s):  
F. Kurz ◽  
T. Plach ◽  
J. Suss ◽  
T. Wagenleitner ◽  
D. Zinner ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Precision ◽  
Wafer Bonding ◽  
Wafer Level ◽  
3D Ics ◽  
Direct Wafer Bonding ◽  
Bonding Technology

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

TLP Bonding Technologies for Micro Joining and 3D Packaging

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001221-001252 ◽  
Author(s):  
Kei Murayama ◽  
Mitsuhiro Aizawa ◽  
Mitsutoshi Higashi
Keyword(s):  
High Temperature ◽  
Melting Point ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Tlp Bonding ◽  
Hermetic Sealing ◽  
Low Temperature Bonding ◽  
Free Material ◽  
Bonding Technique

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance. The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability. The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered. We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed. In this paper, we report on various possible application of the TLP bonding.

Novel low-temperature CMOS-compatible full-wafer-bonding process for the fabrication of 3D embedded microchannels using SU-8

2004 ◽  
Author(s):  
Francisco J. Blanco ◽  
Maria Agirregabiria ◽  
Maria Tijero ◽  
Javier Berganzo ◽  
Jorge Garcia ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Cmos Compatible

Low-temperature Cu-Cu thermocompression bonding for encapsulation of a MEMS mirror

2019 ◽  
Vol 2019 (NOR) ◽  
pp. 000012-000016
Author(s):  
Henri Ailas ◽  
Jaakko Saarilahti ◽  
Tuomas Pensala ◽  
Jyrki Kiihamäki
Keyword(s):  
Low Temperature ◽  
Bond Strength ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Ex Situ ◽  
High Yield ◽  
Maximum Temperature ◽  
Wafer Level ◽  
Cu Films ◽  
Thermocompression Bonding

Abstract In this study, a low temperature wafer-level packaging process aimed for encapsulating MEMS mirrors was developed. The glass cap wafer used in the package has an antireflective (AR) coating that limits the maximum temperature of the bonding process to 250°C. Copper thermocompression was used as copper has a high self-diffusivity and the native oxidation on copper surfaces can be completely removed with combination of ex situ acetic acid wet-etch and in situ forming gas anneal. Making it suitable for a development of a low temperature bonding process. In this work, bonding on of sputtered and electrodeposited copper films was studied on temperatures ranging from 200°C to 300°C as well as the effect of pretreatment on bond strength. The study presents a successful thermocompression bonding process for sputtered Cu films at a low temperature of 200°C with high yield of 97 % after dicing. The bond strength was recorded to be 75 MPa, well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa. The high dicing yield and bond strength suggest that the thermocompression bonding could be possible even at temperatures below 200°C. However, the minimum bonding temperature was not yet determined in this study.

Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000836-000858 ◽  
Author(s):  
Sang Hwui Lee ◽  
Michael Khbeis
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Yield ◽  
Activation Process ◽  
Wafer Level ◽  
3D Integration ◽  
Release Process ◽  
Adhesive Film ◽  
Die Set ◽  
Commercial Off The Shelf

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

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