A Novel Backside Gate Structure to Improve Device Performance

2015 ◽  
Vol 66 (1) ◽  
pp. 185-190
Author(s):  
Y.-H. Hwang ◽  
W. Zhu ◽  
C. Dong ◽  
S. Ahn ◽  
F. Ren ◽  
...  
Keyword(s):  
Device Performance ◽  
Gate Structure ◽  
Improve Device

A Recessed-Gate In0.52Al0.48As/n+-In0.53Ga0.47As Misfet

1988 ◽  
Vol 144 ◽  
Author(s):  
Jesús A. del Alamo ◽  
Takashi Mizutani
Keyword(s):  
High Performance ◽  
Current Gain ◽  
Device Performance ◽  
Promising Candidate ◽  
Gate Structure ◽  
Source Resistance ◽  
Heavily Doped ◽  
Recessed Gate ◽  
Improve Device ◽  
A Current

ABSTRACTScaling of the In0.52Al0.48As insulator thickness of In0.52Al0.48As/n+-In0.53Ga0.47As MIStype FET's is experimentally found to result in a drastic drop of performance below 200 Å. This is demonstrated to arise from an increase in the sheet resistance of the extrinsic portions of the device that accompanies insulator scaling. In order to solve this problem, a recessed-gate dopedchannel MISFET with a very thin (300 Å) n+-In0.53Ga0.47As cap layer has been fabricated. A 1.5 μm long gate device showed a transconductance of 285 mS/mm and a current-gain cut-off frequency of 19.4 GHz. This result proves the ability of a thin n+-In0.53Ga0.47As cap to reduce source resistance and improve device performance. The fabricated recessed-gate structure is a promising candidate for high-performance scaled MIS-type FET's based on thin, heavily-doped In0.53Gav0.47 As channels.

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

2006 ◽  
Vol 913 ◽  
Author(s):  
Young Way Teh ◽  
John Sudijono ◽  
Alok Jain ◽  
Shankar Venkataraman ◽  
Sunder Thirupapuliyur ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Dielectric Film ◽  
High Stress ◽  
Significant Degree ◽  
Strain Effect ◽  
Device Performance ◽  
Hot Carrier ◽  
Tcad Simulation ◽  
Improve Device ◽  
Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

scholarly journals Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 654
Author(s):  
Shouyi Wang ◽  
Qi Zhou ◽  
Kuangli Chen ◽  
Pengxiang Bai ◽  
Jinghai Wang ◽  
...  
Keyword(s):  
Hole Concentration ◽  
Drain Current ◽  
Device Performance ◽  
Depletion Effect ◽  
Threshold Voltages ◽  
Gate Structure ◽  
Drain Side ◽  
Effective Reduction ◽  
Field Peak ◽  
Thin Barrier

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

Slow surface passivation and crystal relaxation with additives to improve device performance and durability for tin-based perovskite solar cells

2018 ◽  
Vol 11 (9) ◽  
pp. 2353-2362 ◽  
Author(s):  
Efat Jokar ◽  
Cheng-Hsun Chien ◽  
Amir Fathi ◽  
Mohammad Rameez ◽  
Yu-Hao Chang ◽  
...  
Keyword(s):  
Solar Cells ◽  
Power Conversion Efficiency ◽  
Conversion Efficiency ◽  
Surface Passivation ◽  
Power Conversion ◽  
Perovskite Solar Cells ◽  
Device Performance ◽  
Slow Surface ◽  
Effective Additive ◽  
Improve Device

Ethylenediammonium diiodide (EDAI2) served as an effective additive for tin-based perovskite solar cells to attain a power conversion efficiency approaching 9%.

TEM Study of Amorphous Silicon Recrystallization

1999 ◽  
Vol 5 (S2) ◽  
pp. 754-755
Author(s):  
Lawrence K Lam ◽  
Nan Jiang ◽  
Dieter G Ast ◽  
John Silcox
Keyword(s):  
Amorphous Silicon ◽  
Oxide Layer ◽  
Crystalline Silicon ◽  
Silicon Layer ◽  
Nickel Silicide ◽  
Device Performance ◽  
Thermal Budget ◽  
Temperature Oxide ◽  
Lateral Crystallization ◽  
Improve Device

Recently there has been increasing interest in nickel induced lateral recrystallization of amorphous silicon because of its potential to improve device performance and to lower the thermal budget during processing. The hypothesis is that the formation of nickel silicide provides a low energy nucleus for the recrystallization of amorphous silicon. The silicide, moving into a-Si, leaves crystalline silicon behind.1 The grains formed, therefore, tend to elongated. In this paper, we attempt to use TEM to investigate in detail the nickel assisted lateral crystallization of amorphous silicon. The sample was prepared by first depositing a 1000A thick low temperature, oxide layer, LTO, on Corning 1737 glass. A 1000A thick amorphous silicon layer, a-Si, and 1000A thick a-Si were deposited subsequently. The sample was pattern and etched with hydrofluoric acid to form lOum x lOum holes in the oxide layer. Next, 200A of nickel was evaporated onto the sample, followed by a 600°C, 6 hours anneal to induce lateral recrystallization.

Evaluation of Degradation due to Electron Irradiation of Si1-xCx S/D n-type MOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 1197-1200
Author(s):  
Masato Hori ◽  
Yuki Asai ◽  
Masashi Yoneoka ◽  
Isao Tsunoda ◽  
Kenichiro Takakura ◽  
...  
Keyword(s):  
Electron Irradiation ◽  
Electron Mobility ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Enhancement Effect ◽  
Device Performance ◽  
Irradiation Effects ◽  
Radiation Induced ◽  
Improve Device

To solve the problem of the limitation to improve device performance in standard Si integration technologies and to develop radiation-harsh devices, the irradiation effects of Si1-xCx source/drain (S/D) n-type metal oxide semiconductor field effect transistors (n-MOSFETs) have been investigated. It is shown that the drain current and the maximum electron mobility of Si1-xCx n-MOSFETs decrease by electron irradiation. The reduction of the device performance can be explained by the radiation-induced lattice defects in the devices. However, the electron mobility enhancement effect by adding C remained after an electron irradiation up to 5×1017 e/cm2.

Selenization of Sb2Se3 absorber layer: An efficient step to improve device performance of CdS/Sb2Se3 solar cells

2014 ◽  
Vol 105 (8) ◽  
pp. 083905 ◽  
Author(s):  
Meiying Leng ◽  
Miao Luo ◽  
Chao Chen ◽  
Sikai Qin ◽  
Jie Chen ◽  
...  
Keyword(s):  
Solar Cells ◽  
Absorber Layer ◽  
Device Performance ◽  
Improve Device

scholarly journals Physical Modeling of Graphene Nanoribbon FET- Quantum Mechanics

2020 ◽  
Vol 9 (3) ◽  
pp. 3230-3235
Keyword(s):  
Physical Modeling ◽  
Device Simulation ◽  
Graphene Nanoribbon ◽  
Device Performance ◽  
Double Gate ◽  
Lithography Process ◽  
And Performance ◽  
Near Future ◽  
Improve Device ◽  
Non Equilibrium Green’S Function

limited by scaling challenges of CMOS devices, the option to improve device performance is to look for novel materials and devices. Carbon, Carbon nanotubes (CNT) and graphene are prominent contenders for substituting silicon in near future. Graphene nanoribbon (GNR) which share many of the fascinating electrical and mechanical properties of CNT are a suitable device material because of compatibility with lithography process. A double gate GNRFET is simulated by solving quantum transport equation with self-consistent electrostatics, while incorporating non-parabolic band structure of GNRFET. Non equilibrium Green’s function (NEGF) approach is used for device simulation. This paper provides physical modeling of GNRFET and investigates the device characteristics and performance for different families of GNRs as well as for different GNR widths.

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