scholarly journals A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors

2021 ◽  
Vol 17 (3) ◽  
pp. 1-44
Author(s):  
Heewoo Kim ◽  
Aporva Amarnath ◽  
Javad Bagherzadeh ◽  
Nishil Talati ◽  
Ronald G. Dreslinski
Keyword(s):  
Integrated Circuits ◽  
System Design ◽  
High Speed ◽  
High Mobility ◽  
Cmos Technology ◽  
System Level ◽  
Software Designers ◽  
Technical Content ◽  
Basic Vocabulary ◽  
Silicon Cmos

The advancement of Silicon CMOS technology has led information technology innovation for decades. However, scaling transistors down according to Moore’s law is almost reaching its limitations. To improve system performance, cost, and energy efficiency, vertical-optimization in multiple layers of the computing stack is required. Technological awareness in terms of devices and circuits could enable informed system-level decisions. For example, graphene is a promising material for extremely scaled high-speed transistors because of its remarkably high mobility, but it can not be used in integrated circuits as a result of the high leakage current from its zero bandgap. In this article, we discuss the fundamental physics of transistors and their ramifications on system design to assist device-level technology consideration during system design. Additionally, various emerging devices and their utilization on a vertically-optimized computing stack are introduced. This article serves as a survey of emerging device technologies that may be relevant in these areas, with an emphasis on making the descriptions approachable by system and software designers to understand the potential solutions. A basic vocabulary will be built to understand how to digest technical content, followed by a survey of devices, and finally a discussion of the implications for future processing systems.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A modified prefix operator well suited for area-efficient brick-based adder implementations

2011 ◽  
Vol 9 ◽  
pp. 289-295
Author(s):  
I. Rust ◽  
T. G. Noll
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Short Circuit ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Classical Operator ◽  
Signal Combination ◽  
Short Circuit Currents ◽  
Prefix Adders ◽  
Sub Wavelength

Abstract. The implementation of integrated circuits becomes more and more difficult in the Ultra-Deep-Submicron regime due to sub-wavelength lithography issues. An approach called Brick-Based Design was recently proposed to eliminate the disadvantages of staying with the classical approach to layout design. Prefix adders are a core component in a wide variety of applications due to their high speed and regular topology. In this paper, a modified prefix operator for prefix adders is proposed which is well suited for brick-style layout implementation and, in addition, offers an increase in efficiency. The proposed operator makes it possible to use a mirror gate for the generation of both generate and propagate signals, which exhibits a forbidden input signal combination. This "forbidden state" causes an increase in power dissipation due to transient short circuit currents. The effect of the forbidden state was quantified as part of a comparison against the classical prefix operator, based on 64-bit Sklansky adders implemented in a 40-nm CMOS technology. The effects of the forbidden state were found to be well acceptable. The implementation of the adder based on the proposed prefix operator reduces the area by 29% while increasing the power by 13% compared to one based on the classical operator.

scholarly journals Photo thermal effect graphene detector featuring 105 Gbit s−1 NRZ and 120 Gbit s−1 PAM4 direct detection

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
S. Marconi ◽  
M. A. Giambra ◽  
A. Montanaro ◽  
V. Mišeikis ◽  
S. Soresi ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Direct Detection ◽  
Chemical Vapour ◽  
High Mobility ◽  
Optical Power ◽  
Pulse Amplitude ◽  
Thermo Electric ◽  
Available Bandwidth ◽  
Voltage Amplifier

AbstractOne of the main challenges of next generation optical communication is to increase the available bandwidth while reducing the size, cost and power consumption of photonic integrated circuits. Graphene has been recently proposed to be integrated with silicon photonics to meet these goals because of its high mobility, fast carrier dynamics and ultra-broadband optical properties. We focus on graphene photodetectors for high speed datacom and telecom applications based on the photo-thermo-electric effect, allowing for direct optical power to voltage conversion, zero dark current, and ultra-fast operation. We report on a chemical vapour deposition graphene photodetector based on the photo-thermoelectric effect, integrated on a silicon waveguide, providing frequency response >65 GHz and optimized to be interfaced to a 50 Ω voltage amplifier for direct voltage amplification. We demonstrate a system test leading to direct detection of 105 Gbit s−1 non-return to zero and 120 Gbit s−1 4-level pulse amplitude modulation optical signals.

scholarly journals VLC Network Design for High Mobility Users in Urban Tunnels

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 88
Author(s):  
Edmundo Torres-Zapata ◽  
Victor Guerra ◽  
Jose Rabadan ◽  
Martin Luna-Rivera ◽  
Rafael Perez-Jimenez
Keyword(s):  
Network Design ◽  
Intelligent Transportation Systems ◽  
High Speed ◽  
Vehicular Networks ◽  
Low Cost ◽  
High Mobility ◽  
Visible Light Communication ◽  
Transportation Systems ◽  
System Level ◽  
On The Road

Current vehicular systems require real-time information to keep drivers safer and more secure on the road. In addition to the radio frequency (RF) based communication technologies, Visible Light Communication (VLC) has emerged as a complementary way to enable wireless access in intelligent transportation systems (ITS) with a simple design and low-cost deployment. However, integrating VLC in vehicular networks poses some fundamental challenges. In particular, the limited coverage range of the VLC access points and the high speed of vehicles create time-limited links that the existing handover procedures of VLC networks can not be accomplished timely. Therefore, this paper addresses the problem of designing a vehicular VLC network that supports high mobility users. We first modify the traditional VLC network topology to increase uplink reliability. Then, a low-latency handover scheme is proposed to enable mobility in a VLC network. Furthermore, we validate the functionality of the proposed VLC network design method by using system-level simulations of a vehicular tunnel scenario. The analysis and the results show that the proposed method provides a steady connection, where the vehicular node is available more than 99% of the time regardless of the number of vehicular nodes on this network. Additionally, the system is able to achieve a Frame-Error-Rate (FER) performance lower than 10−3.

scholarly journals Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos Technology

2012 ◽  
Vol 19 (2) ◽  
pp. 191-202
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz ◽  
Stanisław Szczepański ◽  
Robert Piotrowski
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Cmos Technology ◽  
Image Sensor ◽  
Early Vision ◽  
Vision Processing ◽  
Measurement Results ◽  
Speed Up ◽  
Image Processing Algorithms ◽  
Image Processors

Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos TechnologyThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 μm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 × 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.

scholarly journals Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Bandwidth Extension ◽  
High Compliance ◽  
Compensation Methods ◽  
Inductive Peaking ◽  
Cascode Current Mirror

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

scholarly journals Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 432 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Karel Appels ◽  
Szymon Kulis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Digital Integrated Circuits ◽  
Physical Implementation ◽  
Radiation Hard ◽  
Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

ACE16k: A 128×128 FOCAL PLANE ANALOG PROCESSOR WITH DIGITAL I/O

2003 ◽  
Vol 13 (06) ◽  
pp. 427-434 ◽  
Author(s):  
GUSTAVO LIÑAN CEMBRANO ◽  
ANGEL RODRÍGUEZ-VÁZQUEZ ◽  
SERVANDO ESPEJO MEANA ◽  
RAFAEL DOMÍNGUEZ-CASTRO
Keyword(s):  
Focal Plane ◽  
High Speed ◽  
Cmos Technology ◽  
System Level ◽  
Early Vision ◽  
External Data ◽  
Data Interchange ◽  
Analog Processor ◽  
New Generation ◽  
And Control

This paper presents a new generation 128×128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35μm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

A System-Level Correction SAR ADC with Noise-Tolerant Technique

2018 ◽  
Vol 27 (13) ◽  
pp. 1850202
Author(s):  
Daiguo Xu ◽  
Kaikai Xu ◽  
Shiliu Xu ◽  
Lu Liu ◽  
Tao Liu
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Sar Adc ◽  
System Level ◽  
Small Noise ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
The Core ◽  
Measurement Results ◽  
Noise Tolerant

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.

scholarly journals Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1936
Author(s):  
Karel Appels ◽  
Jeffrey Prinzie
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Cmos Technology ◽  
Digital Logic ◽  
Radiation Environment ◽  
Digital Integrated Circuits ◽  
Distributed Approach ◽  
Implementation Methodology ◽  
Logic Cells ◽  
Radiation Tolerant

This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.

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