scholarly journals Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Bandwidth Extension ◽  
High Compliance ◽  
Compensation Methods ◽  
Inductive Peaking ◽  
Cascode Current Mirror

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

scholarly journals A low-noise current preamplifier in 120 nm CMOS technology

2008 ◽  
Vol 6 ◽  
pp. 213-217 ◽  
Author(s):  
H. Uhrmann ◽  
W. Gaberl ◽  
H. Zimmermann
Keyword(s):  
High Speed ◽  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Special Focus ◽  
Current Mirror ◽  
Chip Area ◽  
The Impact

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

DESIGN LOW VOLTAGE CURRENT MIRROR AT 32NM REGIME

2017 ◽  
Vol 5 (1) ◽  
pp. 16
Author(s):  
Avinash Sukadeo Pawar
Keyword(s):  
Power Supply ◽  
High Speed ◽  
High Stability ◽  
Low Voltage ◽  
Current Mirror ◽  
Lower Power ◽  
Speed Performance ◽  
Accurate Performance ◽  
Simulation Results ◽  
Lower Voltage

As the technology moving towards lower voltage for high stability and accurate performance. We design low voltage current mirror using IGFET, FDSOI, CNTFET.These transistor moving towards low-voltage high-speed performance. Here in this paper, we have design low voltage current mirror for Accurate duplication of current. To obtain accurate duplication of current we verify the performance of low voltage current mirror on FDSOI and CNTFET Transistor having 32nm technology.The circuit is simulated with 32nm technology for FDSOI and CNFET. They operate at lower power supply than IGFET. The simulation results show the improvement in knee voltage 1.7v and 1.3v for the current mirror.

scholarly journals A Fast ALU Design in CMOS for Low Voltage Operation

VLSI Design ◽  
2002 ◽  
Vol 14 (4) ◽  
pp. 315-327 ◽  
Author(s):  
A. Srivastava ◽  
D. Govindarajan
Keyword(s):  
Delay Time ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Substrate Bias ◽  
Back Gate ◽  
Low Voltage Operation ◽  
Logical Operations ◽  
Ripple Carry Adder ◽  
Speed Advantage

A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in 1.2 μm N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to |0.4| V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design.

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