Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers

2015 ◽  
Vol 2 (1) ◽  
pp. 1-23 ◽  
Author(s):  
Yi Xu ◽  
Bo Zhao ◽  
Youtao Zhang ◽  
Jun Yang
Keyword(s):  
High Throughput ◽  
High Frequency ◽  
Channel Allocation ◽  
Virtual Channel ◽  
On Chip

HIGH SPEED MULTI-RESOURCE ARBITER WITH ACTIVE VIRTUAL CHANNEL ALLOCATION FOR NETWORK ON CHIPS

2010 ◽  
Vol 19 (07) ◽  
pp. 1579-1596 ◽  
Author(s):  
XUGUANG GUAN ◽  
ZHANGMING ZHU ◽  
DUAN ZHOU ◽  
YINTANG YANG
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Channel Allocation ◽  
Cmos Technology ◽  
Virtual Channel ◽  
Large Power ◽  
Virtual Channels ◽  
Allocation Process ◽  
On Chip

To improve the shortcomings of long arbitration–allocation time and large power consumption in conventional network on chips, this paper proposes a high speed multi-resource arbiter with active virtual channel allocation. Through arbitrating the acknowledgement signals of virtual channels, the virtual channels can attend the arbitration–allocation process actively. Thus reduces the virtual channel allocation time. Furthermore, the proposed multi-resource arbiter has integrated the function of virtual channel allocation, which improves the performance and simplifies the design process simultaneously. Null convention logic units are used to make the circuit quasi-delay insensitive and high robustness. The proposed multi-resource arbiter is implemented based on SMIC 0.18 μm standard CMOS technology. Results have shown that the arbitration–allocation time of the arbiter is only 824.1 ps, which reduced 25.1% compared with the conventional one. The power consumption and the area are slightly larger than the conventional ones. The proposed high speed multi-resource arbiter is suitable for high performance and high robustness interconnections of on chip networks.

Design of Network Adapter Compatible OCP for High-Throughput NOC

2013 ◽  
Vol 313-314 ◽  
pp. 1341-1346 ◽  
Author(s):  
Jian Wang ◽  
Zhi Jia Yang
Keyword(s):  
High Throughput ◽  
Interconnection Network ◽  
Virtual Channel ◽  
Address Space ◽  
Communication Performance ◽  
Satisfactory Performance ◽  
Global Address Space ◽  
Ip Cores ◽  
On Chip ◽  
Interface Protocol

Network adapter is one of the most important components of NOC which is recommended to be used in present and future SOCs. In this paper, a network adapter compatible with OCP interface protocol is designed to enable the integration of IP cores from different providers into an on-chip interconnection network. In order to tradeoff communication performance with complication, the design of network adapter is based on a single global address space and supports burst transmission and virtual channel technology. With the goal of reducing transport latency, the processes of encapsulation and decapsulation are executing simultaneously with packet transmitting and receiving. Considering the simulation result, the network adapter presented in this paper gets satisfactory performance.

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