The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers

2010 ◽  
Author(s):  
Son Truong Nguyen ◽  
Shigeru Oyanagi
Keyword(s):  
High Performance ◽  
Channel Allocation ◽  
Low Cost ◽  
Virtual Channel ◽  
On Chip

HIGH SPEED MULTI-RESOURCE ARBITER WITH ACTIVE VIRTUAL CHANNEL ALLOCATION FOR NETWORK ON CHIPS

2010 ◽  
Vol 19 (07) ◽  
pp. 1579-1596 ◽  
Author(s):  
XUGUANG GUAN ◽  
ZHANGMING ZHU ◽  
DUAN ZHOU ◽  
YINTANG YANG
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Channel Allocation ◽  
Cmos Technology ◽  
Virtual Channel ◽  
Large Power ◽  
Virtual Channels ◽  
Allocation Process ◽  
On Chip

To improve the shortcomings of long arbitration–allocation time and large power consumption in conventional network on chips, this paper proposes a high speed multi-resource arbiter with active virtual channel allocation. Through arbitrating the acknowledgement signals of virtual channels, the virtual channels can attend the arbitration–allocation process actively. Thus reduces the virtual channel allocation time. Furthermore, the proposed multi-resource arbiter has integrated the function of virtual channel allocation, which improves the performance and simplifies the design process simultaneously. Null convention logic units are used to make the circuit quasi-delay insensitive and high robustness. The proposed multi-resource arbiter is implemented based on SMIC 0.18 μm standard CMOS technology. Results have shown that the arbitration–allocation time of the arbiter is only 824.1 ps, which reduced 25.1% compared with the conventional one. The power consumption and the area are slightly larger than the conventional ones. The proposed high speed multi-resource arbiter is suitable for high performance and high robustness interconnections of on chip networks.

Design and Calibration of MIMU Based on Chip Size Micro Inertial Sensors

2013 ◽  
Vol 849 ◽  
pp. 302-309
Author(s):  
Yun Xu ◽  
Xin Hua Zhu ◽  
Yu Wang
Keyword(s):  
High Performance ◽  
Inertial Sensors ◽  
Low Cost ◽  
Rapid Development ◽  
Experimental Result ◽  
Integrated Navigation ◽  
Bias Stability ◽  
Chip Size ◽  
Order Of Magnitude ◽  
On Chip

With rapid development of micro fabrication technology, the performance of MIMU has gradually improved. The MIMU introduced in this paper is based on the silicon micro machined gyroscope of type MSG7000D and accelerometer of type MSA6000. The volume of it is 3×3×3cm3, the mass is 68.5g and the power consumption is less than 1w. The experimental result shows that the bias stability of the gyroscope and accelerometer for each axis of the designed MIMU is less than 10°/h and 0.5mg respectively. For the non orthogonality in three axes of the structure, MIMU needs to be calibrated. After calibration, the measurement accuracy has improved by an order of magnitude. The designed MIMU can satisfy the requirement of high performance, low cost, light weight and small size for strap-down navigation system, thus it can be widely applied not only to the field of vehicles integrated navigation, attitude measurement but also to the fields of personal goods such as mobile, game consoles and so on.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Application of WeChat Mini-Program and Wi-Fi SoC in Agricultural IoT: A Low-Cost Greenhouse Monitoring System

2020 ◽  
Vol 63 (2) ◽  
pp. 325-337
Author(s):  
Lei Zhou ◽  
Zhengjun Qiu ◽  
Yong He
Keyword(s):  
Internet Of Things ◽  
Monitoring System ◽  
High Performance ◽  
Low Cost ◽  
Rapid Development ◽  
Sensor Nodes ◽  
Sensor Data ◽  
Smart Devices ◽  
Increasing Demand ◽  
On Chip

HighlightsA quick solution for developing and deploying custom agricultural IoT systems is proposed.Low-cost and high-performance devices are used for the design of sensor nodes.A mobile application based on WeChat Mini-Program is developed for device and data management.The proposed system brings convenience to both users and developers.Abstract. Increasing demand for automatic management of agricultural production and real-time remote monitoring has increased the need for smart devices, wireless technologies, and sensors. The internet of things (IoT) has emerged as a common technology for the management of multiple devices by multiple users. Some professional solutions are relatively difficult to implement for researchers who are interested in agricultural IoT but do not have requisite skills in computers and electronics. The unfriendliness of the user software limits the practical application of agricultural IoT in China. This article presents a simple solution based on an SoC (system-on-chip) and WeChat mini-program that focuses on low-cost hardware, rapid development, user-friendly application design, and helping developers get a quick start in building a DIY monitoring system. The ESP8266, a high-performance SoC, is used as the microcontroller and Wi-Fi module to transfer the sensor data to a remote server. A WeChat mini-program provides the graphical user interface, enabling users to manage devices and access data by clicking. Users can log into the system using their WeChat accounts and bind devices by scanning QR codes on the devices. Thus, the complex management and device binding in conventional systems can be overcome. The system is easy to be expand and has great potential for greenhouse environmental monitoring in China. Keywords: Greenhouse ambient monitoring, Internet of things, WeChat mini-program, Wi-Fi SoC.

scholarly journals Low-Cost Allocator Implementations for Networks-on-Chip Routers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10
Author(s):  
Min Zhang ◽  
Chiu-Sing Choy
Keyword(s):  
Low Cost ◽  
Virtual Channel ◽  
Careful Study ◽  
Network Simulator ◽  
Networks On Chip ◽  
Look Ahead ◽  
Generic Architecture ◽  
On Chip ◽  
The Look ◽  
The Impact

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

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