Simultaneous depth and area minimization in LUT-based FPGA mapping

Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays - FPGA '95 ◽

10.1145/201310.201322 ◽

1995 ◽

Cited By ~ 6

Author(s):

Jason Cong ◽

Yean-Yow Hwang

Keyword(s):

Area Minimization

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ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.931 ◽

2014 ◽

Vol E97.A (4) ◽

pp. 931-939

Author(s):

Bu-Ching LIN ◽

Juinn-Dar HUANG ◽

Jing-Yang JOU

Keyword(s):

Area Minimization ◽

Constant Multiplication

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Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401139 ◽

2021 ◽

Author(s):

Ria Rashid ◽

Nandakumar Nambath

Keyword(s):

Particle Swarm Optimization ◽

Optimization Algorithm ◽

Particle Swarm Optimization Algorithm ◽

Particle Swarm ◽

Swarm Optimization ◽

Hybrid Particle ◽

Hybrid Particle Swarm Optimization ◽

Area Minimization

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An adaptive selection approach for the 2D rectangle packing area minimization problem

Omega ◽

10.1016/j.omega.2017.09.002 ◽

2018 ◽

Vol 80 ◽

pp. 22-30 ◽

Cited By ~ 2

Author(s):

Lijun Wei ◽

Wenbin Zhu ◽

Andrew Lim ◽

Qiang Liu ◽

Xin Chen

Keyword(s):

Minimization Problem ◽

Adaptive Selection ◽

Rectangle Packing ◽

Area Minimization ◽

Selection Approach

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Clock cycle estimation based on dead time and control unit area minimization

Microprocessing and Microprogramming ◽

10.1016/0165-6074(94)90048-5 ◽

1994 ◽

Vol 40 (10-12) ◽

pp. 821-824 ◽

Cited By ~ 1

Author(s):

H. Mecha ◽

M. Fernández ◽

R. Hermida ◽

D. Mozos ◽

K. Olcoz

Keyword(s):

Dead Time ◽

Unit Area ◽

Clock Cycle ◽

Control Unit ◽

Area Minimization ◽

And Control

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Area minimization in a three-sided switchbox by sliding the modules

IEEE Transactions on Computers ◽

10.1109/12.61050 ◽

1990 ◽

Vol 39 (11) ◽

pp. 1395-1398

Author(s):

M. Sarrafzadeh

Keyword(s):

Area Minimization

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An improved heuristic algorithm for 2D rectangle packing area minimization problems with central rectangles

Engineering Applications of Artificial Intelligence ◽

10.1016/j.engappai.2017.08.012 ◽

2017 ◽

Vol 66 ◽

pp. 1-16 ◽

Cited By ~ 2

Author(s):

Lei Wu ◽

Xue Tian ◽

Jixu Zhang ◽

Qi Liu ◽

Wensheng Xiao ◽

...

Keyword(s):

Heuristic Algorithm ◽

Rectangle Packing ◽

Minimization Problems ◽

Area Minimization

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Balanced Power, Speed and Area Minimization of Finite State Machines for FPGA Devices

Computer Information Systems and Industrial Management - Lecture Notes in Computer Science ◽

10.1007/978-3-030-28957-7_39 ◽

2019 ◽

pp. 469-480

Author(s):

Adam Klimowicz

Keyword(s):

Finite State Machines ◽

State Machines ◽

Area Minimization ◽

Finite State

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Design and Enactment of Dynamically Reconfigurable Bus Enhanced NoC Architecture for Emerging Digital System

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.f1268.0986s319 ◽

2019 ◽

Vol 8 (6S3) ◽

pp. 1501-1504

Keyword(s):

Structural Design ◽

Essential Element ◽

Power Reduction ◽

Digital System ◽

Architecture Design ◽

Vlsi Circuit ◽

Dynamically Reconfigurable ◽

Rail Network ◽

Area Minimization

The large amount imperative issue in present VLSI circuit proposes in the area and power reduction. This work proposes a new architecture which reduces an area efficiently.The reimbursement of adding a little latency, modified mutual bus as an essential element of the NoC structural design is explored. This architecture design reduces the charge of partisan a broad choice of design occurrence through specified throughput needs by minimizing the requirement of design entities in the architecture design of NoC road and rail network for the area minimization.

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