Area minimization for hierarchical floorplans

Algorithmica ◽  
1996 ◽  
Vol 15 (6) ◽  
pp. 550-571 ◽  
Author(s):  
Peichen Pan ◽  
Weiping Shi ◽  
C. L. Liu
Keyword(s):  
Area Minimization

An adaptive selection approach for the 2D rectangle packing area minimization problem

Omega ◽  
2018 ◽  
Vol 80 ◽  
pp. 22-30 ◽  
Author(s):  
Lijun Wei ◽  
Wenbin Zhu ◽  
Andrew Lim ◽  
Qiang Liu ◽  
Xin Chen
Keyword(s):  
Minimization Problem ◽  
Adaptive Selection ◽  
Rectangle Packing ◽  
Area Minimization ◽  
Selection Approach

Clock cycle estimation based on dead time and control unit area minimization

1994 ◽  
Vol 40 (10-12) ◽  
pp. 821-824 ◽  
Author(s):  
H. Mecha ◽  
M. Fernández ◽  
R. Hermida ◽  
D. Mozos ◽  
K. Olcoz
Keyword(s):  
Dead Time ◽  
Unit Area ◽  
Clock Cycle ◽  
Control Unit ◽  
Area Minimization ◽  
And Control

scholarly journals Design and Enactment of Dynamically Reconfigurable Bus Enhanced NoC Architecture for Emerging Digital System

2019 ◽  
Vol 8 (6S3) ◽  
pp. 1501-1504
Keyword(s):  
Structural Design ◽  
Essential Element ◽  
Power Reduction ◽  
Digital System ◽  
Architecture Design ◽  
Vlsi Circuit ◽  
Dynamically Reconfigurable ◽  
Rail Network ◽  
Area Minimization

The large amount imperative issue in present VLSI circuit proposes in the area and power reduction. This work proposes a new architecture which reduces an area efficiently.The reimbursement of adding a little latency, modified mutual bus as an essential element of the NoC structural design is explored. This architecture design reduces the charge of partisan a broad choice of design occurrence through specified throughput needs by minimizing the requirement of design entities in the architecture design of NoC road and rail network for the area minimization.

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

2012 ◽  
Vol 47 (3) ◽  
pp. 757-768 ◽  
Author(s):  
Chia-Hsiang Yang ◽  
Tsung-Han Yu ◽  
Dejan Markovic
Keyword(s):  
3Gpp Lte ◽  
Area Minimization
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