ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication

Author(s):  
Bu-Ching LIN ◽  
Juinn-Dar HUANG ◽  
Jing-Yang JOU
Author(s):  
Tonjam Gunendra Singh ◽  
Kuldeep Thingbaijam ◽  
Basanta Nameirakpam

Omega ◽  
2018 ◽  
Vol 80 ◽  
pp. 22-30 ◽  
Author(s):  
Lijun Wei ◽  
Wenbin Zhu ◽  
Andrew Lim ◽  
Qiang Liu ◽  
Xin Chen

1994 ◽  
Vol 40 (10-12) ◽  
pp. 821-824 ◽  
Author(s):  
H. Mecha ◽  
M. Fernández ◽  
R. Hermida ◽  
D. Mozos ◽  
K. Olcoz

The large amount imperative issue in present VLSI circuit proposes in the area and power reduction. This work proposes a new architecture which reduces an area efficiently.The reimbursement of adding a little latency, modified mutual bus as an essential element of the NoC structural design is explored. This architecture design reduces the charge of partisan a broad choice of design occurrence through specified throughput needs by minimizing the requirement of design entities in the architecture design of NoC road and rail network for the area minimization.


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