scholarly journals High-bandwidth data memory systems for superscalar processors

1991 ◽  
Author(s):  
Gurindar S. Sohi ◽  
Manoj Franklin
Keyword(s):  
Memory Systems ◽  
Superscalar Processors ◽  
Data Memory ◽  
High Bandwidth

scholarly journals High-bandwidth data memory systems for superscalar processors

1991 ◽  
Vol 26 (4) ◽  
pp. 53-62 ◽  
Author(s):  
Gurindar S. Sohi ◽  
Manoj Franklin
Keyword(s):  
Memory Systems ◽  
Superscalar Processors ◽  
Data Memory ◽  
High Bandwidth

scholarly journals High-bandwidth data memory systems for superscalar processors

1991 ◽  
Vol 25 (Special Issue) ◽  
pp. 53-62 ◽  
Author(s):  
Gurindar S. Sohi ◽  
Manoj Franklin
Keyword(s):  
Memory Systems ◽  
Superscalar Processors ◽  
Data Memory ◽  
High Bandwidth

Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems

2019 ◽  
Vol 68 (5) ◽  
pp. 646-659
Author(s):  
Hsing-Min Chen ◽  
Shin-Ying Lee ◽  
Trevor Mudge ◽  
Carole-Jean Wu ◽  
Chaitali Chakrabarti
Keyword(s):  
Memory Systems ◽  
High Bandwidth

Overview and Technical Trend of Chain FeRAM

2010 ◽  
Vol 1250 ◽  
Author(s):  
Daisaburo Takashima
Keyword(s):  
Marketing Strategy ◽  
High Speed ◽  
Low Voltage ◽  
Disk Drive ◽  
Memory Systems ◽  
Ferroelectric Capacitor ◽  
Performance Improvements ◽  
Cell Signal ◽  
Low Voltage Operation ◽  
High Bandwidth

AbstractA chain FeRAMTM is the best solution to realize high-speed and high-bandwidth nonvolatile RAM with low power dissipation. In this paper, the overview of chain FeRAM, the technical trend for FeRAM scaling and the marketing strategy are presented. First of all, the concept and performance of chain FeRAM are described. Secondly, the status and history of chain FeRAM development are presented. Thirdly, four kinds of scaling strategies for chain FeRAM are presented; (1) A shrink trend of chain cell including a capacitor plug shared with twin cells, and process techniques including Ir/TiAlN-barrier metal and MOCVD-PZT with SrRuO3 electrode, which are installed in 16Kb, 8Mb, 32Mb, 64Mb and 128Mb chain FeRAMs, (2) Capacitor damage suppression processes to reinforce step coverage and protect H2 damage even in 0.1μm2 capacitor of 128Mb, (3) A scalable array architecture such as an octal / quad bitline architecture to reduce bitline capacitance and ensure enough cell signal in scaled ferroelectric capacitor, and (4) A ferroelectric capacitor overdrive technique by driving shield-bitlines to enlarge tail-to-tail cell signal in low voltage operation of 1.3V. Fourthly, future direction of chain FeRAM is discussed. The vertical capacitor is one of candidates for gigabit-scale chain FeRAMs, and solves signal problem and achieves small 4F2 cell without contact formation. Finally, the marketing strategy to take full advantage of chain FeRAM is presented. A nonvolatile FeRAM cache is the promising candidate to achieve high bandwidth memory systems. Applications of chain FeRAM to solid-state drive (SSD) and hard-disk drive (HDD) and their system performance improvements are demonstrated.

Design challenges in Interposer based 3-D Memory Logic Interface

2015 ◽  
Vol 2015 (1) ◽  
pp. 000050-000054
Author(s):  
Andy Heinig ◽  
Muhammad Waqas Chaudhary ◽  
Robert Fischbach ◽  
Michael Dittrich
Keyword(s):  
System Performance ◽  
High Performance ◽  
Memory Systems ◽  
Design Problems ◽  
Hybrid Memory ◽  
High Bandwidth ◽  
Performance System ◽  
Memory Type ◽  
Metal Layers ◽  
3D Memory

Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. In this paper we look at interposer-based and stacked solutions to integrate processor and 3D memory into a high performance system. The comparison is made for different technological decisions, design problems faced for choosing a certain 3D memory type from Wide IO/1–2, High bandwidth memory (HBM) and Hybrid Memory Cube (HMC). Logic die size, metal layers and material of interposer affected by routing requirements of memory systems are discussed.

Language processing is not a race against time

2016 ◽  
Vol 39 ◽  
Author(s):  
Giosuè Baggio ◽  
Carmelo M. Vicario
Keyword(s):  
Information Processing ◽  
Human Brain ◽  
Language Processing ◽  
Cognitive Functions ◽  
Memory Systems ◽  
Language System ◽  
Moderating Factors

AbstractWe agree with Christiansen & Chater (C&C) that language processing and acquisition are tightly constrained by the limits of sensory and memory systems. However, the human brain supports a range of cognitive functions that mitigate the effects of information processing bottlenecks. The language system is partly organised around these moderating factors, not just around restrictions on storage and computation.

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