A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

Positive-to-negative subthreshold swing of a MOSFET tuned by the ferroelectric switching dynamics of BiFeO3

Ferroelectricity can reduce the subthreshold swing (SS) of metal-oxide-semiconductor field-effect transistors (MOSFETs) to below the room-temperature Boltzmann limit of ~60 mV/dec and provides an important strategy to achieve a steeper SS. Surprisingly, by carefully tuning the polarization switching dynamics of BiFeO3 ferroelectric capacitors the SS of a commercial power MOSFET can even be tuned to zero or a negative value, i.e., the drain current increases with a constant or decreasing gate voltage. In particular, in addition to the positive SS of lower than 60 mV/dec, the zero and negative SS can be established with a drain current spanning for over seven orders of magnitude. These intriguing phenomena are explained by the ferroelectric polarization switching dynamics, which change the charge redistributions and accordingly affect the voltage drops across the ferroelectric capacitor and MOSFET. This study provides deep insights into understanding the steep SS in ferroelectric MOSFETs, which could be promising for designing advanced MOSFETs with an ultralow and tunable SS.

Optimization of the In Situ Biasing FIB Sample Preparation for Hafnia-Based Ferroelectric Capacitor

Hafnia-based ferroelectric (FE) thin films have received extensive attention in both academia and industry, benefitting from their outstanding scalability and excellent CMOS compatibility. Hafnia-based FE capacitors in particular have the potential to be used in dynamic random-access memory (DRAM) applications. Obtaining fine structure characterization at ultra-high spatial resolution is helpful for device performance optimization. Hence, sample preparation by the focused ion beam (FIB) system is an essential step, especially for in situ biasing experiments in a transmission electron microscope (TEM). In this work, we put forward three tips to improve the success rate of in situ biasing experiments: depositing a carbon protective layer to position the interface, welding the sample on the top of the Cu column of the TEM grid, and cutting the sample into a comb-like shape. By these means, in situ biasing of the FE capacitor was realized in TEM, and electric-field-induced tetragonal (t-) to monoclinic (m-) structure transitions in Hf0.5Zr0.5O2 FE film were observed. The improvement of FIB sample preparation technology can greatly enhance the quality of in situ biasing TEM samples, improve the success rate, and extend from capacitor sample preparation to other types.

Impact of Rapid-Thermal-Annealing Temperature on the Polarization Characteristics of a PZT-Based Ferroelectric Capacitor

A metal-ferroelectric-metal (MFM) capacitor was fabricated to investigate the effect of the rate-of-change of temperature in the rapid thermal annealing (RTA) process on the physical properties of the MFM capacitor’s ferroelectric layer [lead zirconate oxide (PZT)]. Remnant polarization (2 × Pr) is measured and monitored while performing the RTA process at 500 °C–700 °C. It turned out that, for a given target/final temperature in the RTA process, 2Pr of the ferroelectric layer decreases with a higher rate-of-change of temperature. This can provide a way to adjust the properties of the PZT layer, depending on the RTA process condition (i.e., using various rate-of-changes of temperature) for a given final/target temperature.