Temperature Effects of Constant Bias Stress on n-Channel FETs with Hf-based Gate Dielectric

2005 ◽  
Vol 44 (4B) ◽  
pp. 2201-2204 ◽  
Author(s):  
Rino Choi ◽  
Byoung Hun Lee ◽  
Chadwin D. Young ◽  
Jang Hoan Sim ◽  
Gennadi Bersuker
Keyword(s):  
Temperature Effects ◽  
Gate Dielectric ◽  
Bias Stress ◽  
Constant Bias

Temperature effects of constant bias stress on NFETs with Hf-based gate dielectric

2004 ◽  
Author(s):  
Rino Choi ◽  
Byoung Hun Lee ◽  
Chadwin D. Young ◽  
Jang Hoan Sim ◽  
Gennadi Bersuker
Keyword(s):  
Temperature Effects ◽  
Gate Dielectric ◽  
Bias Stress ◽  
Constant Bias

Towards Understanding the Interaction Between Hydrogen Poisoning and Bias Stress in AlGaN/GaN MIS-HEMTs with SiNx Gate Dielectric

2021 ◽  
pp. 1-1
Author(s):  
Rui Gao ◽  
Chang Liu ◽  
Zhiyuan He ◽  
Yiqiang Chen ◽  
Yijun Shi ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Bias Stress

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

2016 ◽  
Vol 108 (3) ◽  
pp. 033502 ◽  
Author(s):  
Yu-Hong Chang ◽  
Ming-Jiue Yu ◽  
Ruei-Ping Lin ◽  
Chih-Pin Hsu ◽  
Tuo-Hung Hou
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Positive Bias ◽  
Bias Stress ◽  
Al2o3 Gate Dielectric

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

Performance of Polycrystalline Silicon Thin Film Transistors with Double Layer Gate Dielectric

1992 ◽  
Vol 284 ◽  
Author(s):  
Ji-Ho Kung ◽  
Miltiadis K. Hatalis ◽  
Jerzy Kanicki
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Silicon Dioxide ◽  
Double Layer ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Nitride Layer ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Effective Carrier

ABSTRACTThe electrical characteristics of n- and p-channel poly-Si thin film transistors having a double layer gate dielectric structure are reported. The gate dielectric consists of a silicon dioxide layer and a nitrogen-rich silicon nitride layer, both deposited by PECVD at low temperatures (≥400° C). When the silicon nitride was in contact with the poly-Si film, the effective carrier mobility (μeff), threshold voltage (Vth and subthreshold swing (St) for n-channel devices were 36 cm2/Vsec, -1.8 V and 1.65 V/decade, respectively, while for p-channel devices were 6 cm2/Vsec, -37 and 2.47 V/decade, respectively. These devices were not stable under negative gate bias stress, due to the injection of holes into the silicon nitride. When silicon dioxide was in contact with the poly-Si film, the μeff, Vth and St for n-channel devices were 26 cm2/Vsec, 3 V and 1.63 V/decade, respectively, while for p-channel devices were 10 cm2/Vsec, -22 V and 1.52 V/decade, respectively. These devices were stable under d.c. bias stress.

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