Constant Bias Stress Effects on Threshold Voltage of Pentacene Thin-Film Transistors Employing Polyvinylphenol Gate Dielectric

2007 ◽  
Vol 28 (10) ◽  
pp. 874-876 ◽  
Author(s):  
Tae Ho Kim ◽  
Chung Kun Song ◽  
Jin Seong Park ◽  
Min Chul Suh
2019 ◽  
Vol 28 (8) ◽  
pp. 088502
Author(s):  
Chao-Yang Han ◽  
Yuan Liu ◽  
Yu-Rong Liu ◽  
Ya-Yi Chen ◽  
Li Wang ◽  
...  

2016 ◽  
Vol 108 (3) ◽  
pp. 033502 ◽  
Author(s):  
Yu-Hong Chang ◽  
Ming-Jiue Yu ◽  
Ruei-Ping Lin ◽  
Chih-Pin Hsu ◽  
Tuo-Hung Hou

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.


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