High Speed Integrated Circuit Technology

10.1142/4716 ◽  
2001 ◽  
Author(s):  
Mark Rodwell
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Circuit Technology

scholarly journals Wire Laying Methods as an Alternative to Multilayer PCB's

1984 ◽  
Vol 11 (2) ◽  
pp. 117-122
Author(s):  
G. Messner ◽  
P. Plonski ◽  
A. Martens
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Impedance Control ◽  
Vlsi Circuits ◽  
High Density ◽  
Large Numbers ◽  
Design And Manufacturing ◽  
Computer Based ◽  
Board Performance ◽  
Circuit Technology

The rapid growth of integrated circuit technology, culminating in VLSI circuits, is responsible for the proliferation of new, surface mountable device packages with large numbers of input-output terminals. Conventional printed circuit or multilayer techniques have been driven to the technological edge in the effort to interconnect these new types of packages. Because the etched conductors can be replaced with fine, insulated wires, automated high density discrete wiring techniques can provide easier high density interconnections and with shorter turn-around times. Among the dozen or so presently available discrete wiring techniques, the fastest growing is Multiwire®. Multiwire is a computer based design and manufacturing system, where special machines are precisely laying down polyimide insulated wires over adhesive coated substrates having etched power and ground planes. The finished boards exhibit microstrip characteristics, providing impedance control for high speed applications. The manufacturing process and Multiwire board performance capabilities are described in this paper.

Si/SiGe and III-V Integrated Circuit Technology for Next Generation High-Speed Systems: Comparisons and Tradeoffs

1998 ◽  
Vol 535 ◽  
Author(s):  
Lawrence E. Larson
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Next Generation ◽  
Circuit Technology

AbstractThis paper will summarize the technology tradeoffs that are involved in the implementation of high-speed integrated circuit technology for communications applications. The advantages of Si/SiGe and III-V technology with respect to CMOS and Si bipolar technologies are discussed.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

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