scholarly journals Wire Laying Methods as an Alternative to Multilayer PCB's

1984 ◽  
Vol 11 (2) ◽  
pp. 117-122
Author(s):  
G. Messner ◽  
P. Plonski ◽  
A. Martens
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Impedance Control ◽  
Vlsi Circuits ◽  
High Density ◽  
Large Numbers ◽  
Design And Manufacturing ◽  
Computer Based ◽  
Board Performance ◽  
Circuit Technology

The rapid growth of integrated circuit technology, culminating in VLSI circuits, is responsible for the proliferation of new, surface mountable device packages with large numbers of input-output terminals. Conventional printed circuit or multilayer techniques have been driven to the technological edge in the effort to interconnect these new types of packages. Because the etched conductors can be replaced with fine, insulated wires, automated high density discrete wiring techniques can provide easier high density interconnections and with shorter turn-around times. Among the dozen or so presently available discrete wiring techniques, the fastest growing is Multiwire®. Multiwire is a computer based design and manufacturing system, where special machines are precisely laying down polyimide insulated wires over adhesive coated substrates having etched power and ground planes. The finished boards exhibit microstrip characteristics, providing impedance control for high speed applications. The manufacturing process and Multiwire board performance capabilities are described in this paper.

THE DEPOSITION AND CONTROL OF SELF ASSEMBLED SILICON NANO ISLANDS ON CRYSTALLINE SILICON

2008 ◽  
Vol 18 (04) ◽  
pp. 901-910
Author(s):  
RAGNAR KIEBACH ◽  
ZHENRUI YU ◽  
MARIANO ACEVES-MIJARES ◽  
DONGCAI BIAN ◽  
JINHUI DU
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuit ◽  
Crystalline Silicon ◽  
Substrate Surface ◽  
Chemical Vapor ◽  
High Density ◽  
Transmission Electron ◽  
Pressure Chemical ◽  
And Control ◽  
Circuit Technology

The formation of nano sized Si structures during the annealing of silicon rich oxide (SRO) films was investigated. These films were synthesized by low pressure chemical vapor deposition (LPCVD) and used as precursors, a post-deposition thermal annealing leads to the formation of Si nano crystals in the SiO 2 matrix and Si nano islands ( Si nI ) at c-Si /SRO interface. The influences of the excess Si concentration, the incorporation of N in the SRO precursors, and the presence of a Si concentration gradient on the Si nI formation were studied. Additionally the influence of pre-deposition substrate surface treatments on the island formation was investigated. Therefore, the substrate surface was mechanical scratched, producing high density of net-like scratches on the surface. Scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM) were used to characterize the synthesized nano islands. Results show that above mentioned parameters have significant influences on the Si nIs . High density nanosized Si islands can epitaxially grow from the c-Si substrate. The reported method is very simple and completely compatible with Si integrated circuit technology.

scholarly journals Incremental Automatic Correction for Digital VLSI Circuits

2020 ◽  
Author(s):  
Lamya Gaber ◽  
Aziza I. Hussein ◽  
Mohammed Moness
Keyword(s):  
Computer Aided Design ◽  
High Speed ◽  
Negative Impact ◽  
Positive Impact ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Large Numbers ◽  
Aided Design ◽  
The Impact ◽  
Compact Test

The impact of the recent exponential increase in complexity of digital VLSI circuits has heavily affected verification methodologies. Many advances toward verification and debugging techniques of digital VLSI circuits have relied on Computer Aided Design (CAD). Existing techniques are highly dependent on specialized test patterns with specific numbers increased by the rising complexity of VLSI circuits. A second problem arises in the form of large sizes of injecting circuits for correction and large number of SAT solver calls with a negative impact on the resultant running time. Three goals arise: first, diminishing dependence on a given test pattern by incrementally generating compact test patterns corresponding to design errors during the rectification process. Second, to reduce the size of in-circuit mutation circuit for error-fixing process. Finally, distribution of test patterns can be performed in parallel with a positive impact on digital VLSI circuits with large numbers of inputs and outputs. The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs of type gate replacements in several digital VLSI circuits from ISCAS'85 with high speed and full accuracy. The speed of proposed Auto-correction mechanism outperforms the latest existing methods around 4.8x using ISCAS'85 benchmarks. The parallel distribution of test patterns on digital VLSI circuits during generating new compact test patterns achieves speed around 1.2x compared to latest methods.

A new CR-delay circuit technology for high-density and high-speed DRAMs

1989 ◽  
Vol 24 (4) ◽  
pp. 905-910 ◽  
Author(s):  
Y. Watanabe ◽  
T. Ohsawa ◽  
K. Sakurai ◽  
T. Furuyama
Keyword(s):  
High Speed ◽  
High Density ◽  
Delay Circuit ◽  
Circuit Technology
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