<title>Fault tolerant techniques for integrated circuits in submicron and nanotechnologies</title>

Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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Modelling of ionization effects and the effects of displacement in digital chips for CAD

Forestry Engineering Journal ◽

10.12737/8491 ◽

2015 ◽

Vol 4 (4) ◽

pp. 280-290 ◽

Cited By ~ 21

Author(s):

Ачкасов ◽

V. Achkasov ◽

Чевычелов ◽

Yu. Chevychelov ◽

Анциферова ◽

...

Keyword(s):

Integrated Circuits ◽

Dose Rate ◽

Fault Tolerant ◽

Neutron Radiation ◽

Operating Mode ◽

Neutron Pulse ◽

X Ray ◽

Ionization Current ◽

Collector Junction ◽

The Impact

The methods of design of digital fault-tolerant bipolar integrated circuits to exposure to radiations such as gamma, x-ray and neutron radiation are considered, as well as the impact of the neutron pulse, which af-fect largely on the gain of the transistor. The operating mode of integrated circuits with change in the ini-tial values of voltages, as well as currents of the emitter and of the base is presented. Numerical calcula-tions of the ionization current in the base-collector junction are considered which allow pre-calculate dose rate of gamma, x-ray and neutron radiation.

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Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits

2011 IEEE International SOC Conference ◽

10.1109/socc.2011.6085088 ◽

2011 ◽

Author(s):

Yi-Xue Zheng ◽

Po-Ping Kan ◽

Liang-Bi Chen ◽

Kai-Yang Hsieh ◽

Bo-Chuan Cheng ◽

...

Keyword(s):

Integrated Circuits ◽

Fault Tolerant ◽

Three Dimensional ◽

Application Specific

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Entanglement across separate silicon dies in a modular superconducting qubit device

npj Quantum Information ◽

10.1038/s41534-021-00484-1 ◽

2021 ◽

Vol 7 (1) ◽

Author(s):

Alysson Gold ◽

J. P. Paquette ◽

Anna Stockklauser ◽

Matthew J. Reagor ◽

M. Sohaib Alam ◽

...

Keyword(s):

Solid State ◽

Integrated Circuits ◽

Large Scale ◽

Fault Tolerant ◽

Bell Inequality ◽

Building Blocks ◽

Superconducting Qubit ◽

Modular Architecture ◽

Near Term ◽

Qubit Gate

AbstractAssembling future large-scale quantum computers out of smaller, specialized modules promises to simplify a number of formidable science and engineering challenges. One of the primary challenges in developing a modular architecture is in engineering high fidelity, low-latency quantum interconnects between modules. Here we demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits, achieving two-qubit gate fidelities as high as 99.1 ± 0.5% and 98.3 ± 0.3% for iSWAP and CZ entangling gates, respectively. The quality of the inter-module entanglement is further confirmed by a demonstration of Bell-inequality violation for disjoint pairs of entangled qubits across the four separate silicon dies. Having proven out the fundamental building blocks, this work provides the technological foundations for a modular quantum processor: technology which will accelerate near-term experimental efforts and open up new paths to the fault-tolerant era for solid state qubit architectures.

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Improved fault tolerance of Turbo decoding based on optimized index assignments

Advances in Radio Science ◽

10.5194/ars-12-187-2014 ◽

2014 ◽

Vol 12 ◽

pp. 187-195 ◽

Cited By ~ 1

Author(s):

J. Geldmacher ◽

J. Götze

Keyword(s):

Integrated Circuits ◽

Communication Systems ◽

Fault Tolerant ◽

Error Resilience ◽

Process Variations ◽

Design Of Algorithms ◽

Turbo Decoder ◽

Index Assignment ◽

Reduced Power Consumption ◽

The Impact

Abstract. This paper investigates the impact of an error-prone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

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