Prediction of interconnect delay variations using pattern matching

2007 ◽  
Author(s):  
Eric Y. Chin ◽  
Juliet A. Holwill ◽  
Andrew R. Neureuther
Keyword(s):  
Pattern Matching ◽  
Interconnect Delay ◽  
Delay Variations

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Pattern Recognition for Classification and Matching of Car Tires

2005 ◽  
Vol 33 (1) ◽  
pp. 2-17 ◽  
Author(s):  
D. Colbry ◽  
D. Cherba ◽  
J. Luchini
Keyword(s):  
Computer Vision ◽  
Feature Extraction ◽  
Pattern Matching ◽  
Fourier Transforms ◽  
Two Dimensions ◽  
Multiple Sources ◽  
Matching Process ◽  
Visual Searches ◽  
New Feature ◽  
2D Fft

Abstract Commercial databases containing images of tire tread patterns are currently used by product designers, forensic specialists and product application personnel to identify whether a given tread pattern matches an existing tire. Currently, this pattern matching process is almost entirely manual, requiring visual searches of extensive libraries of tire tread patterns. Our work explores a first step toward automating this pattern matching process by building on feature analysis techniques from computer vision and image processing to develop a new method for extracting and classifying features from tire tread patterns and automatically locating candidate matches from a database of existing tread pattern images. Our method begins with a selection of tire tread images obtained from multiple sources (including manufacturers' literature, Web site images, and Tire Guides, Inc.), which are preprocessed and normalized using Two-Dimensional Fast Fourier Transforms (2D-FFT). The results of this preprocessing are feature-rich images that are further analyzed using feature extraction algorithms drawn from research in computer vision. A new, feature extraction algorithm is developed based on the geometry of the 2D-FFT images of the tire. The resulting FFT-based analysis allows independent classification of the tire images along two dimensions, specifically by separating “rib” and “lug” features of the tread pattern. Dimensionality of (0,0) indicates a smooth treaded tire with no pattern; dimensionality of (1,0) and (0,1) are purely rib and lug tires; and dimensionality of (1,1) is an all-season pattern. This analysis technique allows a candidate tire to be classified according to the features of its tread pattern, and other tires with similar features and tread pattern classifications can be automatically retrieved from the database.

Parallel Combining Different Approaches to Multi-pattern Matching for Fpga-based Security Systems

2017 ◽  
Vol 5 (1) ◽  
pp. 8-15
Author(s):  
Sergii Hilgurt ◽  
Keyword(s):  
Information Security ◽  
Pattern Matching ◽  
Intrusion Detection System ◽  
Detection System ◽  
Finite Automata ◽  
Network Intrusion Detection ◽  
Security Systems ◽  
Analytical Technique ◽  
Network Intrusion ◽  
Pros And Cons

The multi-pattern matching is a fundamental technique found in applications like a network intrusion detection system, anti-virus, anti-worms and other signature- based information security tools. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore’s law, traditional software solutions can no longer keep up. Therefore, hardware approaches are frequently being used by developers to accelerate pattern matching. Reconfigurable FPGA-based devices, providing the flexibility of software and the near-ASIC performance, have become increasingly popular for this purpose. Hence, increasing the efficiency of reconfigurable information security tools is a scientific issue now. Many different approaches to constructing hardware matching circuits on FPGAs are known. The most widely used of them are based on discrete comparators, hash-functions and finite automata. Each approach possesses its own pros and cons. None of them still became the leading one. In this paper, a method to combine several different approaches to enforce their advantages has been developed. An analytical technique to quickly advance estimate the resource costs of each matching scheme without need to compile FPGA project has been proposed. It allows to apply optimization procedures to near-optimally split the set of pattern between different approaches in acceptable time.

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