Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

2007 ◽  
Author(s):  
Mosin Mondal ◽  
Tamer Ragheb ◽  
Xiang Wu ◽  
Adnan Aziz ◽  
Yehia Massoud
Keyword(s):  
Interconnect Delay ◽  
Delay Variations ◽  
On Chip

Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

2014 ◽  
pp. 399-419
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Internal Communication ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Delay Variations ◽  
On Chip

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

2011 ◽  
Vol 2 (4) ◽  
pp. 1-20
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Misaligned Data ◽  
Delay Variations ◽  
On Chip

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

2012 ◽  
Vol 3 (4) ◽  
pp. 42-56 ◽  
Author(s):  
Sebastian Höppner ◽  
Dennis Walter ◽  
Georg Ellguth ◽  
René Schüffny
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Error Rates ◽  
Oxide Semiconductor ◽  
Multiprocessor System ◽  
Semiconductor Technology ◽  
Clock Jitter ◽  
Measurement Results ◽  
Delay Variations ◽  
On Chip

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect.

Prediction of interconnect delay variations using pattern matching

2007 ◽  
Author(s):  
Eric Y. Chin ◽  
Juliet A. Holwill ◽  
Andrew R. Neureuther
Keyword(s):  
Pattern Matching ◽  
Interconnect Delay ◽  
Delay Variations
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