Application of full-chip level optical proximity correction to memory device with sub-0.10-μm design rule and ArF lithography

2001 ◽  
Author(s):  
Hyoung-Soon Yune ◽  
Hee-Bom Kim ◽  
Wan-Ho Kim ◽  
Chang-Nam Ahn ◽  
Young-Mog Ham ◽  
...  
Keyword(s):  
Memory Device ◽  
Design Rule ◽  
Optical Proximity Correction

Application of full-chip optical proximity correction for sub-60-nm memory device in polarized illumination

2007 ◽  
Author(s):  
Hyoung-Soon Yune ◽  
Yeong-Bae Ahn ◽  
Dong-jin Lee ◽  
James Moon ◽  
Byung-Ho Nam ◽  
...  
Keyword(s):  
Memory Device ◽  
Optical Proximity Correction

Issues and Challenges of Chemical Mechanical Polishing for Nano-scale Memory Manufacturing

2009 ◽  
Vol 1157 ◽  
Author(s):  
Choon Kun Ryu ◽  
Jonghan Shin ◽  
Hyungsoon Park ◽  
Nohjung Kwak ◽  
Kwon Hong ◽  
...  
Keyword(s):  
Vertical Integration ◽  
Removal Rate ◽  
Memory Device ◽  
Design Rule ◽  
Integration Scheme ◽  
New Materials ◽  
Degree Of Control ◽  
High Removal Rate ◽  
Cu Cmp ◽  
Nano Size

AbstractAs the design rule of memory devices is scaled down to nanoscale, the number of the CMP process has increased considerably due to the complexity of integration scheme. The CMP for isolation has increased significantly because the isolation process of metal contact plugs and damascene metallization at nanoscale has been successfully enabled by the CMP. The CMP selectivity, which depends strongly on the chemistry of the slurry, must be tuned for the various new materials. Recently, in order to get over the limitation in lateral shrinkage of the memory device, several emerging applications have been investigated extensively. A vertical integration needs the new CMP process such as high removal rate Cu CMP. Next generation memories need the CMP process for new materials such as GeSbTe, conductive oxide, and magnetic materials. Since any nano-size scratch will be a killer defect at the nanoscale memory, both the CMP equipment and the consumables must be maintained with tighter degree of control specifications.

Read and Write Operations of Memory Device Consisting of Nonlinear MEMS Resonator

2014 ◽  
Vol 1 ◽  
pp. 352-355 ◽  
Author(s):  
Atsushi YAO ◽  
Takashi HIKIHARA
Keyword(s):  
Memory Device ◽  
Mems Resonator

Tunable Quantum Confinement Effect on Non-volatile Thin Film Polymer Memory Device

2008 ◽  
Author(s):  
Augustin J. Hong ◽  
Kang L. Wang ◽  
Wei Lek Kwan ◽  
Yang Yang ◽  
Dayanara Parra ◽  
...  
Keyword(s):  
Thin Film ◽  
Quantum Confinement ◽  
Quantum Confinement Effect ◽  
Memory Device ◽  
Confinement Effect ◽  
Film Polymer ◽  
Polymer Memory

Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

2001 ◽  
Author(s):  
DongKwon Jeong ◽  
JuHyeon Ahn ◽  
SangIn Lee ◽  
JooHyuk Chung ◽  
ByungLyul Park ◽  
...  
Keyword(s):  
Process Improvement ◽  
Process Development ◽  
Metal Corrosion ◽  
Pass Rate ◽  
Design Rule ◽  
The Novel ◽  
Corrosion Loss ◽  
Barrier Metal ◽  
Development State ◽  
Failure Types

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Application of EMS Analysis to Failure in Cell Area of Memory Device

1998 ◽  
Author(s):  
T. Nukumizu ◽  
J. Sato ◽  
H. Furuya ◽  
H. Namba ◽  
T. Kikuch
Keyword(s):  
Failure Analysis ◽  
Memory Device ◽  
Cell Area

Abstract EMS analysis is widely used in the failure analysis of the semiconductor. Moreover, the availability is widely evaluated. However, EMS analysis is not often used for the defect (1 Bit failure, Word Line failure, Bit Line failure, etc.) in the cell area in the memory device, because information on Fail Bit Map can be facilitated. Recently, make minutely advancing, and it is impossible to detect the defective cause only by Fail Bit Map information. We found the effectiveness as follows by the use of EMS analysis for a defective sample with Fail Bit Map information to solve such a problem. It leads to shortening analysis TAT because a defective part can be specified. Moreover, because the SHORT/OPEN mode can be divided, it is useful for the presumption of a defective mode. Furthermore, it is effective also to the confirmation of the presence of the redundancy and the confirmation of Fail Bit Map. Thus, because the application of EMS analysis for the defect in the cell area of the memory device is very effective to detect a defective cause, I want to recommend it by all means.

Sign in / Sign up

Export Citation Format

Share Document