Electron transport response de-embedding for high-speed image sensors

Author(s):  
Yun-Tzu Chang ◽  
Pol Van Dorpe ◽  
Chris Van Hoof ◽  
Andreas Süss
2000 ◽  
Author(s):  
S. E. Alexandrov ◽  
Gennadii A. Gavrilov ◽  
V. K. Gusev ◽  
E. E. Mukhin ◽  
Galina Y. Sotnikova

Nanophotonics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 497-509 ◽  
Author(s):  
Hideharu Mikami ◽  
Liang Gao ◽  
Keisuke Goda

AbstractHigh-speed optical imaging is an indispensable technology for blur-free observation of fast transient dynamics in virtually all areas including science, industry, defense, energy, and medicine. High temporal resolution is particularly important for microscopy as even a slow event appears to occur “fast” in a small field of view. Unfortunately, the shutter speed and frame rate of conventional cameras based on electronic image sensors are significantly constrained by their electrical operation and limited storage. Over the recent years, several unique and unconventional approaches to high-speed optical imaging have been reported to circumvent these technical challenges and achieve a frame rate and shutter speed far beyond what can be reached with the conventional image sensors. In this article, we review the concepts and principles of such ultrafast optical imaging methods, compare their advantages and disadvantages, and discuss an entirely new class of applications that are possible using them.


2015 ◽  
Vol 15 (8) ◽  
pp. 4365-4372
Author(s):  
Swetha S. George ◽  
Mark F. Bocko ◽  
Zeljko Ignjatovic

1983 ◽  
Author(s):  
Masahiro Mori ◽  
Isao Kondo ◽  
Masakatsu Horie

2015 ◽  
Vol 24 (04) ◽  
pp. 1550054 ◽  
Author(s):  
Jiangtao Xu ◽  
Jing Yu ◽  
Fujun Huang ◽  
Kaiming Nie

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.


2014 ◽  
Vol 35 (10) ◽  
pp. 105008
Author(s):  
Quanliang Li ◽  
Liyuan Liu ◽  
Ye Han ◽  
Zhongxiang Cao ◽  
Nanjian Wu

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