Amorphous-silicon thin-film transistors made at 280°C on clear-plastic substrates by interfacial stress engineering

2007 ◽  
Vol 15 (3) ◽  
pp. 167 ◽  
Author(s):  
Ke Long ◽  
I-Chun Cheng ◽  
Alexis Kattamis ◽  
Helena Gleskova ◽  
Sigurd Wagner ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Interfacial Stress ◽  
Silicon Thin Film ◽  
Plastic Substrates ◽  
Stress Engineering ◽  
Clear Plastic

Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1fabricated at 300°C on Clear Plastic Substrates

2008 ◽  
Vol 1066 ◽  
Author(s):  
Kunigunde H Cherenack ◽  
Alex Z Kattamis ◽  
Bahman Hekmatshoar ◽  
James C Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Fabrication Process ◽  
Plastic Substrate ◽  
Silicon Thin Film ◽  
Free Standing ◽  
Plastic Substrates ◽  
Effective Mobility ◽  
Clear Plastic

ABSTRACTWe have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

Self-Aligned Amorphous Silicon Thin-Film Transistors Fabricated on Clear Plastic at 300 $^{\circ}\hbox{C}$

2010 ◽  
Vol 57 (10) ◽  
pp. 2381-2389 ◽  
Author(s):  
K H Cherenack ◽  
B Hekmatshoar ◽  
James C Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Clear Plastic

Amorphous Silicon Thin-Film Transistors made on Clear Plastic at 300 ¨?C

2009 ◽  
Vol 54 (9(5)) ◽  
pp. 415-420 ◽  
Author(s):  
Kunigunde H. Cherenack ◽  
Alex Z. Kattamis ◽  
Bahman Hekmashoar ◽  
James C. Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Clear Plastic

Amorphous-Silicon Thin-Film Transistors Fabricated at 300 $^{\circ}\hbox{C}$ on a Free-Standing Foil Substrate of Clear Plastic

2007 ◽  
Vol 28 (11) ◽  
pp. 1004-1006 ◽  
Author(s):  
Kunigunde H. Cherenack ◽  
Alex Z. Kattamis ◽  
Bahman Hekmatshoar ◽  
James C. Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Free Standing ◽  
Clear Plastic ◽  
Foil Substrate

Highly stable amorphous-silicon thin-film transistors on clear plastic

2008 ◽  
Vol 93 (3) ◽  
pp. 032103 ◽  
Author(s):  
Bahman Hekmatshoar ◽  
Kunigunde H. Cherenack ◽  
Alex Z. Kattamis ◽  
Ke Long ◽  
Sigurd Wagner ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Clear Plastic

The Instability Characteristics of Amorphous Silicon Thin Film Transistors with Various Interfacial and Bulk Defect States

1997 ◽  
Vol 36 (Part 1, No. 10) ◽  
pp. 6226-6229 ◽  
Author(s):  
Huang-Chung Cheng ◽  
Jun-Wei Tsai ◽  
Chun-Yao Huang ◽  
Fang-Chen Luo ◽  
Hsing-Chien Tuan
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Defect States ◽  
Silicon Thin Film

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

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