Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation

1997 ◽  
Vol 15 (6) ◽  
pp. 2825 ◽  
Author(s):  
Jakub Kedzierski
Keyword(s):  
Silicon Nanowires ◽  
Silicon On Insulator ◽  
Planar Silicon

Bismuth-catalyzed n-type doping and growth evolution of planar silicon nanowires

2020 ◽  
Vol 117 (24) ◽  
pp. 243103
Author(s):  
Taige Dong ◽  
Ying Sun ◽  
Junzhuan Wang ◽  
Jun Xu ◽  
Kunji Chen ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Planar Silicon ◽  
Growth Evolution

Nano-Imprint Patterning of Nanowire Structures for Interconnect Study

2005 ◽  
Author(s):  
Bin Li ◽  
Anastassios Mavrokefalos ◽  
Jianhua Zhou ◽  
Li Shi ◽  
Paul S. Ho ◽  
...  
Keyword(s):  
Electron Beam ◽  
Cross Section ◽  
Silicon Nanowires ◽  
Size Effects ◽  
Silicon On Insulator ◽  
Si Nanowires ◽  
Section Surface ◽  
Etching Mask ◽  
Interconnect Lines ◽  
Nano Imprint

A thermal nano-imprint method has been developed to pattern sub-40 nm polymer lines of Hydrogensilsesquioxane (HSQ) and electron beam resist ZEP 520A. The imprint template was the cross section surface of a selectively etched GaAs/AlGaAs heterostructure wafer. Silicon nanowires were formed using reactive ion etching (RIE) of a silicon-on-insulator wafer with the polymer nanolines as an etching mask. The obtained Si nanowires were well defined and continuous for a length up to hundreds of microns. Reaction of the silicon lines with a metal can lead to the formation of silicide interconnect lines, which is used to investigate the size effects on the transport and electromigration properties of interconnects for future microelectronics.

scholarly journals Synthesis of Planar Reflective Gratings for Silicon Interconnects

2008 ◽  
Vol 2008 ◽  
pp. 1-8
Author(s):  
Ronald Millett ◽  
Jamie Ramsey ◽  
Przemek Bock ◽  
Julie Nkanta ◽  
Henry Schriemer ◽  
...  
Keyword(s):  
Diffraction Grating ◽  
Free Spectral Range ◽  
Silicon On Insulator ◽  
Dispersion Property ◽  
Wavelength Division ◽  
Optical Crosstalk ◽  
Minimal Thickness ◽  
Planar Silicon ◽  
Polarization Insensitive ◽  
Integrated Receiver

The design and simulations of planar reflective gratings for building optical interconnects in silicon-on-insulator (SOI) were studied for a range of silicon core thicknesses of 0.1 to 10 μm. The verticality of the grating facets has been shown to be the main contributing factor to the cumulative crosstalk in thick silicon cores. The dispersion property of the slab was found to limit the minimal thickness of the core for polarization-insensitive gratings. The effects of polarization-dependent confinement on optical crosstalk were studied. The findings were used to design and simulate a polarization-insensitive 18-channel coarse wavelength division demultiplexer (CWDM) with a free spectral range of over 600 nm. The CWDM demultiplexer uses a 1.7 μm silicon core and combines a shallow-etch tapered rib structure and multimode silicon channels to produce box-like passbands for integrated receiver applications. The diffraction grating was constructed using double astigmatic point design with phase-corrected grating facets to reduce astigmatism. Optical properties of the planar gratings have been simulated using quasivectorial diffraction grating theory. The simulation results confirm that there is high diffraction efficiency and low optical crosstalk over the entire range of operation. Applications of planar silicon gratings to the synthesis of silicon interconnects are discussed.

Formation of Single Tiers of Bridging Silicon Nanowires for Transistor Applications Using Vapor-Liquid-Solid Growth from Short Silicon-on-Insulator Sidewalls

Small ◽  
2009 ◽  
Vol 5 (21) ◽  
pp. 2440-2444 ◽  
Author(s):  
Osama M. Nayfeh ◽  
Dimitri A. Antoniadis ◽  
Steven Boles ◽  
Charles Ho ◽  
Carl V. Thompson
Keyword(s):  
Silicon Nanowires ◽  
Silicon On Insulator ◽  
Vapor Liquid Solid ◽  
Vapor Liquid Solid Growth ◽  
Vapor Liquid

Fabrication of SiNWs-FET Nanostructure Via Atomic Force Microscopy Lithography

2020 ◽  
Vol 301 ◽  
pp. 103-110
Author(s):  
Nurain Najihah Alias ◽  
Khatijah Aisha Yaacob ◽  
Kuan Yew Cheong
Keyword(s):  
Atomic Force Microscopy ◽  
Relative Humidity ◽  
Silicon Nanowires ◽  
Silicon Oxide ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Force Microscopy ◽  
Atomic Force ◽  
Effect Transistor ◽  
P Type

The unique electrical properties of silicon nanowires (SiNWs) is one of the reasons it become an attractive transducer for biosensor nowadays. Positive (holes) and negative (electron) charge carriers from SiNWs can simply interact with either positive or negative charge of sensing target. In this paper, we have studied the fabrication of silicon nanowires field effect transistor (SiNWs-FET) nanostructure patterned on 15 Ω resistivity of p-type silicon on insulator (SOI) wafer fabricated via atomic force microscopy lithography technique. To fabricate SiNWs-FET nanostructure, a conductive AFM tip, Cr/Pt cantilever tip, was used then various value of applied voltage, writing speed and relative humidity were studied. Subsequent, followed by wet etching processes, admixture of tetramethylammonium hydroxide (TMAH) and isopropyl alcohol (IPA) were used to remove the undesired of silicon layer and diluted hydrofluoric acid (HF) was used to remove the oxide layer. From the results, it shows that, cantilever tip at 9 V with 0.4 μm/s writing speed and relative humidity between 55% - 60% gives the best formation of silicon oxide to fabricate SiNWs-FET nanostructure.

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