Stability of polycrystalline silicon-on-cobalt disilicide–silicon structures

Author(s):  
S. P. Murarka
2001 ◽  
Vol 670 ◽  
Author(s):  
Hidekazu Sato ◽  
Takae Sukegawa ◽  
Toshifumi Mori ◽  
Kousuke Suzuki ◽  
Haruhisa Mori

ABSTRACTThis paper reports the dependence on the concentration of the germanium (Ge) in polycrystalline silicon (poly-Si) cap layer on the polycrystalline silicon germanium (poly-SiGe) for low resistivity cobalt disilicide (CoSi2) formation. Particularly, we investigate the relationship between sheet resistance of CoSi2 films and concentration of Ge in cap-Si layer. The excellent value of sheet resistance (∼6 / ) is achieved by Ge concentration in cap-Si layer controlled at 2% or less for 90nm length CoSi2/poly-Si/poly-SiGe gate structure. This result indicates that conventional Co silicide process technology can be readily used even for poly-SiGe gate structure.


1982 ◽  
Vol 53 (7) ◽  
pp. 5342-5344 ◽  
Author(s):  
Reda R. Razouk ◽  
Michael E. Thomas ◽  
Sylvia L. Pressacco

1995 ◽  
Vol 5 (2) ◽  
pp. 132-135 ◽  
Author(s):  
M S Benrakkad ◽  
M A Benitez ◽  
J Esteve ◽  
J M Lopez-Villegas ◽  
J Samitier ◽  
...  

2004 ◽  
Vol 96 (12) ◽  
pp. 7568-7573 ◽  
Author(s):  
M. J. H. van Dal ◽  
D. Jawarani ◽  
J. G. M. van Berkum ◽  
M. Kaiser ◽  
J. A. Kittl ◽  
...  

Author(s):  
J. R. Conner ◽  
N. D. Theodore ◽  
S. C. Arney ◽  
C. B. Carter ◽  
N. C. MacDonald

As silicon devices are scaled into the submicron regime, parasitic circuit elements due to wiring and junction capacitance become increasingly significant. One way to reduce these parasitic elements is to fabricate circuits in thin silicon layers on an insulating substrate. Silicon-On-Insulator (SOI) structures can be fabricated by various techniques, including ion implantation of oxygen, recrystallization of amorphous or polycrystalline silicon films deposited on insulating thin films, and oxidation of porous silicon. A new SOI technique, in which islands of silicon become isolated from the silicon substrate during a thermal oxidation step, has been optimized for submicron-width silicon structures. The large stresses associated with the two-dimensional oxidation give rise to the generation and propagation of dislocations in the silicon island during the oxidation sequence. The characterization and removal of these dislocations is an important factor in optimizing these structures.TEM samples have been prepared to evaluate the defect configurations present in these novel submicron SOI structures.


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