scholarly journals An electrothermal model of memory switching in vertical polycrystalline silicon structures

1988 ◽  
Vol 35 (9) ◽  
pp. 1514-1523 ◽  
Author(s):  
V. Malhotra ◽  
J.E. Mahan ◽  
D.L. Ellsworth
Keyword(s):  
Polycrystalline Silicon ◽  
Memory Switching ◽  
Silicon Structures

Memory switching effects in locally grown polycrystalline silicon films

1984 ◽  
Vol 112 (2) ◽  
pp. 121-125 ◽  
Author(s):  
A.G. Abdullayev ◽  
F.D. Kasimov ◽  
V.A. Vetkhov ◽  
V.M. Mamikonova
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Memory Switching ◽  
Polycrystalline Silicon Films ◽  
Locally Grown

Oxidation of tantalum disilicide/polycrystalline silicon structures in dry O2

1982 ◽  
Vol 53 (7) ◽  
pp. 5342-5344 ◽  
Author(s):  
Reda R. Razouk ◽  
Michael E. Thomas ◽  
Sylvia L. Pressacco
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Structures

Stress measurement by microRaman spectroscopy of polycrystalline silicon structures

1995 ◽  
Vol 5 (2) ◽  
pp. 132-135 ◽  
Author(s):  
M S Benrakkad ◽  
M A Benitez ◽  
J Esteve ◽  
J M Lopez-Villegas ◽  
J Samitier ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Stress Measurement ◽  
Silicon Structures ◽  
Microraman Spectroscopy

The relation between phase transformation and onset of thermal degradation in nanoscale CoSi2-polycrystalline silicon structures

2004 ◽  
Vol 96 (12) ◽  
pp. 7568-7573 ◽  
Author(s):  
M. J. H. van Dal ◽  
D. Jawarani ◽  
J. G. M. van Berkum ◽  
M. Kaiser ◽  
J. A. Kittl ◽  
...  
Keyword(s):  
Phase Transformation ◽  
Thermal Degradation ◽  
Polycrystalline Silicon ◽  
Silicon Structures

Transmission electron microscopy of 1/4-micron SOI structures

1988 ◽  
Vol 46 ◽  
pp. 922-923
Author(s):  
J. R. Conner ◽  
N. D. Theodore ◽  
S. C. Arney ◽  
C. B. Carter ◽  
N. C. MacDonald
Keyword(s):  
Electron Microscopy ◽  
Thin Films ◽  
Transmission Electron Microscopy ◽  
Polycrystalline Silicon ◽  
Silicon On Insulator ◽  
Two Dimensional ◽  
Silicon Devices ◽  
Transmission Electron ◽  
Silicon Structures ◽  
Polycrystalline Silicon Films

As silicon devices are scaled into the submicron regime, parasitic circuit elements due to wiring and junction capacitance become increasingly significant. One way to reduce these parasitic elements is to fabricate circuits in thin silicon layers on an insulating substrate. Silicon-On-Insulator (SOI) structures can be fabricated by various techniques, including ion implantation of oxygen, recrystallization of amorphous or polycrystalline silicon films deposited on insulating thin films, and oxidation of porous silicon. A new SOI technique, in which islands of silicon become isolated from the silicon substrate during a thermal oxidation step, has been optimized for submicron-width silicon structures. The large stresses associated with the two-dimensional oxidation give rise to the generation and propagation of dislocations in the silicon island during the oxidation sequence. The characterization and removal of these dislocations is an important factor in optimizing these structures.TEM samples have been prepared to evaluate the defect configurations present in these novel submicron SOI structures.

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