Control of the critical dimensions and line edge roughness with pre-organized block copolymer pixelated photoresists

2009 ◽  
Vol 27 (6) ◽  
pp. 2993 ◽  
Author(s):  
Huiman Kang ◽  
Yun Jun Kim ◽  
Padma Gopalan ◽  
Paul F. Nealey
Keyword(s):  
Block Copolymer ◽  
Line Edge Roughness ◽  
Critical Dimensions ◽  
Edge Roughness

scholarly journals Influence of Additives on the Interfacial Width and Line Edge Roughness in Block Copolymer Lithography

2020 ◽  
Vol 32 (6) ◽  
pp. 2399-2407 ◽  
Author(s):  
Daniel F. Sunday ◽  
Xuanxuan Chen ◽  
Thomas R. Albrecht ◽  
Derek Nowak ◽  
Paulina Rincon Delgadillo ◽  
...  
Keyword(s):  
Block Copolymer ◽  
Line Edge Roughness ◽  
Edge Roughness ◽  
Block Copolymer Lithography ◽  
Copolymer Lithography

Ordering of Self-Assembled Nanodots Improved by Guide Pattern with Low Line Edge Roughness for 5 Tbit/in.2 Patterned Media

2013 ◽  
Vol 596 ◽  
pp. 78-82
Author(s):  
Takuya Komori ◽  
Miftakhul Huda ◽  
Takashi Akahane ◽  
Muneyasu Masuda ◽  
Jing Liu ◽  
...  
Keyword(s):  
Block Copolymer ◽  
High Resolution ◽  
Ammonium Hydroxide ◽  
Line Pattern ◽  
Line Edge Roughness ◽  
Patterned Media ◽  
Tetramethyl Ammonium Hydroxide ◽  
Edge Roughness ◽  
Nanodot Arrays ◽  
Self Assembled

We investigated the possibility of ordering of 12 nm pitced self-assembled nanodots from block copolymer (BCP) improved by the guide pattern with low line edge roughness (LER) for patterned media. We found that LER of the line pattern (σ-value) was reduced by using high-resolution salty development for HSQ resist line pattern fabrication compared with conventional tetramethyl ammonium hydroxide (TMAH) developer. By adopting this development technique to guide pattern fabrication, we demonstrated 10 rows of ordered self-assembled BCP nanodot arrays with a size of 6 nm and a pitch of 12 nm (5 Tbit/in.2) between the guide patterns.

Remediation of Line Edge Roughness in Chemical Nanopatterns by the Directed Assembly of Overlying Block Copolymer Films

2010 ◽  
Vol 43 (5) ◽  
pp. 2334-2342 ◽  
Author(s):  
Mark P. Stoykovich ◽  
Kostas Ch. Daoulas ◽  
Marcus Müller ◽  
Huiman Kang ◽  
Juan J. de Pablo ◽  
...  
Keyword(s):  
Block Copolymer ◽  
Directed Assembly ◽  
Line Edge Roughness ◽  
Copolymer Films ◽  
Edge Roughness

Three-dimensional line edge roughness in pre- and post-dry etch line and space patterns of block copolymer lithography

2020 ◽  
Vol 22 (2) ◽  
pp. 478-488
Author(s):  
Shubham Pinge ◽  
Yufeng Qiu ◽  
Victor Monreal ◽  
Durairaj Baskaran ◽  
Abhaiguru Ravirajan ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
Block Copolymer ◽  
Large Scale ◽  
Three Dimensional ◽  
Coarse Grained ◽  
Line Edge Roughness ◽  
Edge Roughness ◽  
Dry Etch ◽  
Block Copolymer Lithography ◽  
Symmetric Block

In this work, we employ large-scale coarse-grained molecular dynamics (CGMD) simulations to study the three-dimensional line edge roughness associated with line and space patterns of chemo-epitaxially directed symmetric block copolymers.

Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects

2003 ◽  
Author(s):  
Terence Kane ◽  
Michael P. Tenney ◽  
John Bruley
Keyword(s):  
Electrical Characterization ◽  
Short Channel Effects ◽  
Line Edge Roughness ◽  
Short Channel ◽  
Critical Dimensions ◽  
Technology Roadmap ◽  
Transmission Electron ◽  
Edge Roughness ◽  
Channel Effects

Abstract As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.

Modeling Line Edge Roughness in Templated, Lamellar Block Copolymer Systems

2012 ◽  
Vol 45 (23) ◽  
pp. 9507-9516 ◽  
Author(s):  
Paul N. Patrone ◽  
Gregg M. Gallatin
Keyword(s):  
Block Copolymer ◽  
Line Edge Roughness ◽  
Edge Roughness

Line edge roughness measurement technique for fingerprint pattern in block copolymer thin film

2013 ◽  
Author(s):  
Miki Isawa ◽  
Kei Sakai ◽  
Paulina A. Rincon Delgadillo ◽  
Roel Gronheid ◽  
Hiroshi Yoshida
Keyword(s):  
Thin Film ◽  
Block Copolymer ◽  
Measurement Technique ◽  
Line Edge Roughness ◽  
Roughness Measurement ◽  
Edge Roughness ◽  
Fingerprint Pattern
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