Erratum: “Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks” [J. Vac. Sci. Technol. B 24, 1780 (2006)]

2007 ◽  
Vol 25 (1) ◽  
pp. 292
Author(s):  
Parthiban Arunasalam ◽  
Harold D. Ackler ◽  
Bahgat G. Sammakia
Keyword(s):  
Thin Film ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Ultrahigh Density

scholarly journals X-ray nanodiffraction analysis of stress oscillations in a W thin film on through-silicon via

2016 ◽  
Vol 49 (1) ◽  
pp. 182-187 ◽  
Author(s):  
J. Todt ◽  
H. Hammer ◽  
B. Sartory ◽  
M. Burghammer ◽  
J. Kraft ◽  
...  
Keyword(s):  
Thin Film ◽  
Residual Stress ◽  
Finite Element ◽  
Diffraction Data ◽  
Element Model ◽  
Stress Distributions ◽  
Through Silicon Via ◽  
X Ray ◽  
Tangential Stresses ◽  
Stress Components

Synchrotron X-ray nanodiffraction is used to analyse residual stress distributions in a 200 nm-thick W film deposited on the scalloped inner wall of a through-silicon via. The diffraction data are evaluated using a novel dedicated methodology which allows the quantification of axial and tangential stress components under the condition that radial stresses are negligible. The results reveal oscillatory axial stresses in the range of ∼445–885 MPa, with a distribution that correlates well with the scallop wavelength and morphology, as well as nearly constant tangential stresses of ∼800 MPa. The discrepancy with larger stress values obtained from a finite-element model, as well as from a blanket W film, is attributed to the morphology and microstructural nature of the W film in the via.

Wafer-level hermetic vacuum packaging by bonding with a copper–tin thin film sealing ring

2018 ◽  
Vol 28 (4) ◽  
pp. 044002 ◽  
Author(s):  
Teruhisa Akashi ◽  
Hirofumi Funabashi ◽  
Hideki Takagi ◽  
Yoshiteru Omura ◽  
Yoshiyuki Hata
Keyword(s):  
Thin Film ◽  
Vacuum Packaging ◽  
Wafer Level ◽  
Sealing Ring

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Thin Film Packaging for Vacuum MEMS Encapsulation: A Study on Outgassing Phenomenon

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002428-002482
Author(s):  
D. Saint-Patrice ◽  
J. L. Pornin ◽  
B. Savornin ◽  
G. Rodriguez ◽  
S. Danthon ◽  
...  
Keyword(s):  
Thin Film ◽  
Ion Beam ◽  
High Vacuum ◽  
Chip Thickness ◽  
Process Conditions ◽  
Mems Devices ◽  
Wafer Level ◽  
Working Pressure ◽  
Baking Process ◽  
Sealing Materials

Most of the time, MEMS devices require hermetic encapsulation for protection against atmosphere, moisture, particles and standard back-end manufacturing technologies. In the last few years, Wafer Level Packaging (WLP) is moving toward developments on Thin Film Packaging (TFP) in order to save footprint, to reduce chip thickness and packaging costs. In the specific case of high-vacuum MEMS encapsulation (gyro, compass), long term pressure stability is required. As the final performances of these kinds of devices are strongly dependent on the working pressure, using TFP for MEMS encapsulation with controlled vacuum becomes more challenging due to very small cavity volumes. It is then necessary to understand the outgassing phenomenon that take place during TFP encapsulation in order to reduce it. In this paper, our latest developments on thin film packaging technology are presented. Outgassing from materials used in TFP and MEMS devices become key parameters to decrease the pressure inside the package and to improve the reliability. In a first part, pressure and Residual Gas Analysis (RGA) of typical TFP and typical MEMS materials are measured under different time / temperature baking processes. Measurements show that material outgassing mainly comes from H2 and maximum pick appears in the beginning of the thermal process. Thanks to these characterizations, an optimized outgassing baking process in term of time and thermal budget is presented. By minimizing the internal outgassing, materials deposited by PVD sputtering can now be implemented as sealing materials for low pressure MEMS devices. In a second part, specific low temperature Al based materials which has been developed on equipment fully compatible with front-end fab is presented. Multi-layer materials like Ti / Al based materials are compared to our single Al based material to decrease the microstructure size and to improve the sealing performances. Scanning Electronic Microscopy (SEM) and Focused Ion Beam (FIB) cross section characterizations confirm that the grain sizes are highly impacted by sputtering process parameters and a compromise has to be done with MEMS outgassing. Finally, the most suitable outgassing baking process for the inside cavity materials and various Al-based sealing materials and stacks are performed for a MEMS compass device on 200 mm wafers. Pressure inside the cavity less than 10 mbar is obtained and the TFP yield is presented on each process conditions. These results are very promising and showed the capabilities of TFP for vacuum MEMS encapsulation applications despite very small volume cavity. Development of such technology is still under way in order to reach high vacuum level in the range of 10-1 to 10-3 mbar.

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