Self-assembled tungsten nanocrystals in high-k dielectric for nonvolatile memory application

2005 ◽  
Vol 23 (6) ◽  
pp. 2278 ◽  
Author(s):  
S. K. Samanta ◽  
Zerlinda Y. L. Tan ◽  
Won Jong Yoo ◽  
Ganesh Samudra ◽  
Sungjoo Lee ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High K ◽  
Self Assembled ◽  
High K Dielectric

Nonvolatile Memory Characteristics Induced in High-k Dielectric Thin Films through Electron Irradiation

2011 ◽  
Vol 59 (2(2)) ◽  
pp. 726-729 ◽  
Author(s):  
Chan-Rock Park ◽  
Hong-Kyoung Lee ◽  
Jin-Ha Hwang ◽  
Young-Hwan Hahn ◽  
Byeong-Cheol Lee ◽  
...  
Keyword(s):  
Thin Films ◽  
Electron Irradiation ◽  
Nonvolatile Memory ◽  
Dielectric Thin Films ◽  
High K ◽  
High K Dielectric ◽  
Memory Characteristics

scholarly journals Ge nanocrystals in lanthanide-based Lu2O3 high-k dielectric for nonvolatile memory applications

2007 ◽  
Vol 102 (9) ◽  
pp. 094307 ◽  
Author(s):  
M. Y. Chan ◽  
P. S. Lee ◽  
V. Ho ◽  
H. L. Seng
Keyword(s):  
Nonvolatile Memory ◽  
High K ◽  
High K Dielectric ◽  
Memory Applications ◽  
Ge Nanocrystals

Temperature Effects on Charge Transfer Mechanisms of nc-ITO Embedded ZrHfO High-k Nonvolatile Memory Devices

2011 ◽  
Vol 1337 ◽  
Author(s):  
Chia-Han Yang ◽  
Yue Kuo ◽  
Chen-Han Lin ◽  
Way Kuo
Keyword(s):  
Gate Voltage ◽  
Nonvolatile Memory ◽  
Charge Retention ◽  
Mos Capacitors ◽  
Dielectric Thin Film ◽  
High K ◽  
Nonvolatile Memory Devices ◽  
High K Dielectric ◽  
Voltage Region ◽  
Large Charge

ABSTRACTThe nanocrystalline ITO embedded Zr-doped HfO2 high-k dielectric thin film has been made into MOS capacitors for nonvolatile memory studies. The devices showed large charge storage densities, large memory windows, and long charge retention times. In this paper, authors investigated the temperature effect on the charge transport and reliability of this kind of device in the range of 25°C to 125°C. The memory window increased with the increase of the temperature. The temperature influenced the trap and detrap of not only the deeply-trapped but also the loosely-trapped charges. The device lost its charge retention capability with the increase of the temperature. The Schottky emission relationship fitted the device in the positive gate voltage region. However, the Frenkel-Poole mechanism was suitable in the negative gate voltage region.

A Nonvolatile Memory Capacitor Based on a Double Gold Nanocrystal Storing Layer and High-k Dielectric Tunneling and Control Layers

2010 ◽  
Vol 157 (4) ◽  
pp. H463 ◽  
Author(s):  
V. Mikhelashvili ◽  
B. Meyler ◽  
S. Yofis ◽  
J. Salzman ◽  
M. Garbrecht ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High K ◽  
High K Dielectric ◽  
Gold Nanocrystal ◽  
And Control

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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