Minimizing plasma damage and in situ sealing of ultralow-k dielectric films by using oxygen free fluorocarbon plasmas

2005 ◽  
Vol 23 (5) ◽  
pp. 2198 ◽  
Author(s):  
G. Mannaert ◽  
M. R. Baklanov ◽  
Q. T. Le ◽  
Y. Travaly ◽  
W. Boullart ◽  
...  
Keyword(s):  
Dielectric Films ◽  
Plasma Damage ◽  
Fluorocarbon Plasmas

Removing the Barriers to Next Generation'S Dielectric Films: In Situ Void-Free Planarized Films

1990 ◽  
Vol 203 ◽  
Author(s):  
J.R. Monkowski ◽  
M.A. Logan ◽  
L.F. Wright
Keyword(s):  
Aspect Ratio ◽  
Ion Chromatography ◽  
Field Measurements ◽  
Dielectric Films ◽  
Breakdown Field ◽  
Scanning Electron Micrographs ◽  
Aspect Ratios ◽  
New Process ◽  
Scanning Electron

ABSTRACTIn the next generation of semiconductor devices, minimum dimensions will be smaller, aspect ratios (height to width) of devices features will be larger, and BPSG dielectrics will be challenged to deal with these changes. A new process, which integrates deposition, flow, and anneal of BPSG films, and allows void-free filling of high-aspect-ratio trenches with excellent surface planarization, is presented in this paper. Scanning electron micrographs are used to show the extent of film coverage and planarization. Additional characterization includes ion chromatography, ellipsometry, stress measurements, and breakdown field measurements.

Effects of Plasma Damage Removal on Direct Contact Resistance and Hot-Electron-Induced Punch Through (HEIP) of PMOSFETs

2020 ◽  
Vol 20 (11) ◽  
pp. 6622-6626
Author(s):  
Junhwa Song ◽  
Jinhyuk Yoo ◽  
Youngseung Cho ◽  
Jihun Kim ◽  
Jeonghoon Oh ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Direct Contact ◽  
Cost Effective ◽  
Amorphous Layer ◽  
Process Time ◽  
Treatment Technique ◽  
Hot Electron ◽  
Plasma Damage ◽  
Damage Layer

In order to reduce contact resistance (Rc) of the source/drain region in nanoscale devices, it is essential to overcome the increasing leakage and hot-electron-induced punch through (HEIP) degradation. In this paper, we propose a simple in situ Si soft treatment technique immediately after direct contact (DC) etching to reduce Rc and minimize HEIP degradation. We found by analysis with a transmission electron microscope, that 10 s of treatment reduced the plasma damaged layer by 19%, which resulted in 10.5% reduction of the P+ contact resistance. For comparison, the P + Rc was reduced by 6.5% when the doping level of the plug implantation was increased by 25%, but the HEIP breakdown voltage (VHEIP) by AC stress was greatly reduced by more than 80 mV, increasing the standby leakage current of DRAM devices. In the case of removing the plasma damage layer, not only did VHIEP not decrease until after 10 s, but also the reduction in Rc was larger than with the plug enhancement. The effect of the plasma damaged layer on HEIP was verified through the plug effect and gate induced drain leakage measurement, based on the distance between the gate and DC for each process. This simple in situ technique not only removed byproducts and the plasma damaged amorphous layer, but it also affected the effective implantation of dopants in subsequent plug processes. It was also cost effective because the process time was short and no extra process steps were added.

The Oxide/Nitride Interface: a study for gate dielectrics and field passivation

2003 ◽  
Vol 786 ◽  
Author(s):  
B.P. Gila ◽  
B. Luo ◽  
J. Kim ◽  
R. Mehandru ◽  
J.R. LaRoche ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Substrate Surface ◽  
Surface Preparation ◽  
Dielectric Materials ◽  
Ex Situ ◽  
Dielectric Films ◽  
Interface Quality ◽  
Gas Source ◽  
Gas Source Mbe

ABSTRACTThe study of the effects of substrate surface preparation of GaN, both in-situ and ex-situ and the subsequent deposition of dielectric materials is necessary to create a viable GaN FET technology. Surface preparation techniques have been explored using RHEED, AES, SIMS and C-V measurements to produce films of low interface trap density, 1–2E11 eV−1cm−2. A similar study of the as-fabricated HEMT surface was carried out to create a cleaning procedure prior to dielectric passivation. Dielectric films of Sc2O3 and MgO were deposited via gas-source MBE. Post-deposition materials characterization included AES, TEM, XRR and XPS, as well as gate pulse and isolation current measurements for the passivated HEMT devices. From this study, the relationship between the interface structure and chemistry and the quality of the oxide/nitride electrical interface has been determined. The resulting process has led to the near elimination of the current collapse phenomenon. In addition, the resulting oxide/nitride interface quality has allowed for the first demonstration of inversion in GaN.

Nanodiamond/Polyimide High Temperature Dielectric Films for Energy Storage Applications

2013 ◽  
Vol 785-786 ◽  
pp. 410-416
Author(s):  
David H. Wang ◽  
Scott P. Fillery ◽  
Michael F. Durstock ◽  
Li Ming Dai ◽  
Richard A. Vaia ◽  
...  
Keyword(s):  
Dielectric Properties ◽  
Dielectric Loss ◽  
Benzoic Acid ◽  
Surface Functionalization ◽  
High Energy ◽  
High Energy Density ◽  
Dielectric Films ◽  
Benzoic Acid Derivative ◽  
Energy Storage Applications

CP2 polyimide (prepd. from 6FDA and 1,3-bis (3-aminophenoxy) benzene) was blended with (1-50 wt.%) detonation nanodiamonds (DND, pristine, acetone-washed, and 4-(2,4,6-trimethylphenoxy) benzoic acid-functionalized), and the blends were evaluated as thin films for its potential utility in high-energy-density capacitors that would have stable dielectric properties over a wide temperature range (-55 to 300°C) and at frequencies up to or greater than 100 kHz. Both the dielectric storage and loss increased substantially with DND content. Surface functionalization (with the above benzoic acid derivative) significantly reduced the dielectric loss, while the use of acetone-washed DNDs had no effect on the dielectric loss. DND was also blended with CP2 via in-situ polymerization and found to have little effect on the dielectric properties.

Ultra Low-dielectric-constant Materials for 65nm Technology Node and Beyond

2004 ◽  
Vol 812 ◽  
Author(s):  
Hao Cui ◽  
Darren Moore ◽  
Richard Carter ◽  
Masaichi Eda ◽  
Peter Burke ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Dielectric Films ◽  
Low Dielectric Constant ◽  
Plasma Damage ◽  
Pore Characteristics ◽  
Hydrogenated Silicon ◽  
Bonding Structure ◽  
Low Dielectric ◽  
Etch Stop ◽  
Low Dielectric Constant Materials

AbstractPore characteristics including pore size distribution, porosity, and pore interconnectivity of PECVD SiCOH inter- layer dielectric (ILD) materials with different dielectric constant (κ) values have been studied. Oxygen plasma damage to SiCOH low-κ films increases dramatically as the κ value decreases. Simulations showed that, compared to the ILD film, the overhead dielectric films have a significant impact on the overall effective κ (κeff) of the BEOL interconnects. Reducing the κ values of these overhead films helps to alleviate the pressure on the κ value requirement of the ILD materials while still meeting the κeff target. Ultra low-κ (ULK) PECVD hydrogenated silicon carbide (H:SiC) films with a κ of 3.0 have been studied for the etch-stop applications. Studies of the chemical composition and bonding structure suggest that less Si-C networκs are formed and more micro-porosity are incorporated in the ULK H:SiC film. The leakage current of the ULK H:SiC film is found to be about 5 times lower than the H:S iC and H:SiCN films with higher κ values. The etch rate of ULK H:SiC film using a standard SiCOH ILD etch chemistry has been found to be negligible. Such an extremely high etch selectivity maκes these films very good etch-stop layers.

In-situ Rapid Isiheial Pocessing of Thin Epitaxial Dieleciric Films on Silicon and Compound Semi Semiconductors

1986 ◽  
Vol 75 ◽  
Author(s):  
R. Singh ◽  
F. Radpour ◽  
J. Narayan ◽  
S. P. Joshi ◽  
M. Rahati ◽  
...  
Keyword(s):  
Isothermal Annealing ◽  
Structural Characteristics ◽  
Processing Technique ◽  
Dielectric Films ◽  
Light Sources ◽  
Incoherent Light ◽  
Beam System ◽  
Rapid Isothermal Processing

AbstracrWe have developed a new rapid isothermal processing technique for the deposition of epitaxial dielectric films (II–VIa fluorides and their mixtures) on silicon and ccmpound semiconductors. In this process, epitaxial dielectric films are deposited in an e-beam system at room teqperature and subsequently subjected to in-situ rapid isothermal annealing by using incoherent light sources incorporated in the e-beam system. Epitaxial dielectric films of CaF2 and CaxS1−xF2 have been deposited on Si, GaAs and InP. In this paper, prelimilifty results of electrical and structural characteristics of. epitaxial dielectric films on Si and cupourd semiconductors are presented.

Challenges of Ultra Low-k Dielectric Measurement and Plasma Damage Assessment

2006 ◽  
Vol 914 ◽  
Author(s):  
Thomas Abell ◽  
Jeffrey Lee ◽  
Mansour Moinpour
Keyword(s):  
Integrated Circuit ◽  
Dielectric Measurement ◽  
Dielectric Films ◽  
Plasma Damage ◽  
Fast Ion ◽  
Rc Delay ◽  
Destructive Measurement ◽  
Non Destructive ◽  
Low K ◽  
Physical Principles

AbstractThe implementation of porous low-k and ultra-low k dielectrics to reduce RC delay in integrated circuit interconnect wiring has been fraught with numerous challenges. The obvious challenges of materials design and preservation of the desired electrical and mechanical properties upon subsequent processing have been significant. The vulnerability of these films to damage from fast ion and radiation damage will be discussed in the context of post-deposition processing (including low-k cure and plasma processing damage). This paper attempts to review the challenges associated with destructive and non-destructive measurement of low k dielectric films with respect to underlying physical principles of the metrology. Metrology techniques, assumed to be non-destructive based on experience with dense silicon dioxide, will be discussed with regards to newer and more fragile low-k dielectric films.

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