Thermal Management of Ultra Intense Hot Spots With Two-Phase Multi-Microchannels and Embedded Thermoelectric Cooling

Author(s):  
Jackson B. Marcinichen ◽  
Brian P. d’Entremont ◽  
John R. Thome ◽  
Gary Bulman ◽  
Jay Lewis ◽  
...  

This study concerns cooling of electronic components of intense background heat flux with one ultra intense hot spot (e.g. 1000 Wcm−2 on a footprint of 1 cm × 1 cm with 5000 Wcm−2 applied to a 0.02 cm × 0.02 cm region at the center). To manage these extreme heat fluxes and consequently surpass the thermal-hydrodynamic challenges and design paradigms, for example as specified in a recent DARPA request for proposals (Intrachip/Interchip Enhanced Cooling Fundamentals - ICECool Fundamentals [1]), on-chip two-phase multi-microchannel cooling integrated with a superlattice (SL) thin-film thermoeletric cooling (TEC) technology was investigated via computer simulations. The simulations showed that increasing TEC electrical current results in greater enhancement of heat flow through the TEC, but at high currents this benefit is offset by a net addition of heat to the system, which must also be evacuated by the microchannels. When optimized, a minimum peak junction temperature of about 86 °C for a current of about 8 A was found, which represented a reduction of about 4 °C from a maximum allowed 90 °C at the ultra-intense hot-spot, thus potentially significantly capable of exceeding the DARPA [1] requirement, due to the embedded SL TEC within the microevaporator (ME) structure.

Author(s):  
Enes Tamdogan ◽  
Mehmet Arik ◽  
M. Baris Dogruoz

With the recent advances in wide band gap device technology, solid-state lighting (SSL) has become favorable for many lighting applications due to energy savings, long life, green nature for environment, and exceptional color performance. Light emitting diodes (LED) as SSL devices have recently offered unique advantages for a wide range of commercial and residential applications. However, LED operation is strictly limited by temperature as its preferred chip junction temperature is below 100 °C. This is very similar to advanced electronics components with continuously increasing heat fluxes due to the expanding microprocessor power dissipation coupled with reduction in feature sizes. While in some of the applications standard cooling techniques cannot achieve an effective cooling performance due to physical limitations or poor heat transfer capabilities, development of novel cooling techniques is necessary. The emergence of LED hot spots has also turned attention to the cooling with dielectric liquids intimately in contact with the heat and photon dissipating surfaces, where elevated LED temperatures will adversely affect light extraction and reliability. In the interest of highly effective heat removal from LEDs with direct liquid cooling, the current paper starts with explaining the increasing thermal problems in electronics and also in lighting technologies followed by a brief overview of the state of the art for liquid cooling technologies. Then, attention will be turned into thermal consideration of approximately a 60W replacement LED light engine. A conjugate CFD model is deployed to determine local hot spots and to optimize the thermal resistance by varying multiple design parameters, boundary conditions, and the type of fluid. Detailed system level simulations also point out possible abatement techniques for local hot spots while keeping light extraction at maximum.


Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.


2012 ◽  
Vol 134 (5) ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.


2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.


Author(s):  
Etienne Costa-Patry ◽  
Stefano Nebuloni ◽  
Jonathan Olivier ◽  
John Richard Thome
Keyword(s):  
Hot Spot ◽  
On Chip ◽  

Author(s):  
Horacio Nochetto ◽  
Peng Wang ◽  
Avram Bar-Cohen

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.


Author(s):  
Stephen A. Solovitz

Microchannel heat transfer is commonly applied in the thermal management of high-power electronics. Most designs involve a series of parallel microchannels, which are typically analyzed by assuming a uniform flow distribution. However, many devices have a nonuniform thermal distribution, with hot spots producing much higher heat fluxes and temperatures than the baseline. Although solutions have been developed to improve local heat transfer, these are advanced methods using embedded cooling devices. As an alternative, a passive solution is developed here using analytical methods to optimize the channel geometry for a desired, nonuniform flow distribution. This results in a simple power law for the passage diameter, which may be useful for many microfluidic systems, including electronics cooling devices. Computational simulations are then applied to demonstrate the effectiveness of the power law for laminar conditions. At low Reynolds numbers, the flow distribution can be controlled to good accuracy, matching the desired distribution to within less than 1%. Further simulations consider the control of hot spots in laminar developing flow. Under these circumstances, temperatures can be made uniform to within 2 °C over a range of Reynolds numbers (60 to 300), demonstrating the capability of this power law solution.


Author(s):  
Sung-Yong Park ◽  
Jiangtao Cheng ◽  
Chung-Lung (C.-L. ) Chen

Electrowetting-on-dielectric (EWOD) has attracted as one of the effective on-chip cooling technologies. It enables rapid transport of coolant droplets and heat transfer from target heat sources, while consuming extremely low power for fluid transport. However, a sandwiched configuration in conventional EWOD devices only allows sensible heat transfer, which very limits heat transfer capability of the device. In this paper, we report a novel single-sided EWOD (SEWOD) technology that enables two-phase cooling on a single-sided plate. As a result, heat transfer capability of the SEWOD device can be significantly enhanced. A complete set of droplet manipulation functions necessary for active hot spot cooling has been achieved on SEWOD. Hot spot surface modification to hydrophilic makes a droplet stick on a hot spot and maximize its contact area, greatly improving thermal rejection capability of the device. We have demonstrated two-phase cooling on SEWOD. With successive transportation of four droplets with a volume of 30 μL, the hot spot temperature that was initially heated up to 172°C was able to be stably maintained below 100 °C for 475s. This novel SEWOD-driven cooling technique promises to potentially function as a wickless vapor chamber with enhanced thermal managing capabilities.


2008 ◽  
Vol 130 (12) ◽  
Author(s):  
Je-Young Chang ◽  
Ravi S. Prasher ◽  
Suzana Prstic ◽  
P. Cheng ◽  
H. B. Ma

This paper reports the test results of vapor chambers using copper post heaters and silicon die heaters. Experiments were conducted to understand the effects of nonuniform heating conditions (hot spots) on the evaporative thermal performance of vapor chambers. In contrast to the copper post heater, which provides ideal heating, a silicon chip package was developed to replicate more realistic heat source boundary conditions of microprocessors. The vapor chambers were tested for hot spot heat fluxes as high as 746 W/cm2. The experimental results show that evaporator thermal resistance is not sensitive to nonuniform heat conditions, i.e., it is the same as in the uniform heating case. In addition, a model was developed to predict the effective thickness of a sintered-wick layer saturated with water at the evaporator. The model assumes that the pore sizes in the sintered particle wick layer are distributed nonuniformly. With an increase of heat flux, liquid in the larger size pores are dried out first, followed by drying of smaller size pores. Statistical analysis of the pore size distribution is used to calculate the fraction of the pores that remain saturated with liquid at a given heat flux condition. The model successfully predicts the experimental results of evaporative thermal resistance of vapor chambers for both uniform and nonuniform heat fluxes.


Author(s):  
Peng Wang ◽  
Avram Bar-Cohen

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.


Sign in / Sign up

Export Citation Format

Share Document