Impact of Material Properties on Cooling COP of Integrated Thermoelectric Microcoolers

2013 ◽  
Author(s):  
Yee Rui Koh ◽  
Kazuaki Yazawa ◽  
Ali Shakouri
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuit ◽  
Hot Spot ◽  
Coefficient Of Performance ◽  
Total Power ◽  
Vapor Compression ◽  
Total Power Consumption ◽  
On Chip ◽  
The Individual ◽  
The Impact

Thermoelectric (TE) microcooling is promising for removing hotspots in integrated circuit chips. The cooling coefficient-of-performance (COP) of the on-chip thin film or superlattice micro-cooler (SLC) is a metric for assessing the energy efficiency of the hot spot removal. The COP is key for lowering total power consumption and minimizing heat sinking requirements. Due to the moderate performance compared to vapor compression cycles, researchers have devoted considerable effort to improving the figure-of-merit (ZT) of the material over the past decade. However, the impact of each of the individual thermoelectric properties has not been studied separately. We report our study based on an analytical model and analysis results that show the intrinsic impact of electrical conductivity, the Seebeck coefficient, and thermal conductivity, while the device thickness and the drive current are optimized for maximizing cooling COP. The results show that the power factor of the TE materials is a more important parameter than thermal conductivity reduction for improving the cooling performance of the on chip SLC.

scholarly journals Low-Threshold, High-Power On-Chip Tunable III-V/Si Lasers with Integrated Semiconductor Optical Amplifiers

2021 ◽  
Vol 11 (23) ◽  
pp. 11096
Author(s):  
Joan Manel Ramírez ◽  
Pierre Fanneau de la Horie ◽  
Jean-Guy Provost ◽  
Stéphane Malhouitre ◽  
Delphine Néel ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Optical Networks ◽  
Optical Amplifiers ◽  
Semiconductor Optical Amplifiers ◽  
Optical Amplifier ◽  
Silicon On Insulator ◽  
Total Power ◽  
Multiple Quantum ◽  
Total Power Consumption ◽  
On Chip

Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical amplifier in a heterogeneous platform that combines AlGaInAs multiple quantum wells (MQWs) and InP-based materials with silicon-on-insulator (SOI) wafers containing photonic integrated circuits. The co-integrated device is compact, has a total device footprint of 0.5 mm2, a lasing current threshold of 10 mA, a selectable wavelength tuning range of 50 nm centered at λ = 1549 nm, a fiber-coupled output power of 10 mW, and a laser linewidth of ν = 259 KHz. The SOA provides an on-chip gain of 18 dB/mm. The total power consumption of the co-integrated devices remains below 0.5 W even for the most power demanding lasing wavelengths. Apart from the above-mentioned applications, the co-integration of compact widely tunable III-V/Si lasers with on-chip SOAs provides a step forward towards the development of highly efficient, portable, and low power systems for wavelength division multiplexed passive optical networks (WDM-PONs).

scholarly journals Fault detection in HVAC systems using a distribution considering uncertainties

2019 ◽  
Vol 111 ◽  
pp. 05010
Author(s):  
Shohei Miyata ◽  
Yasunori Akashi ◽  
Jongyeon Lim ◽  
Yasuhiro Kuwahara
Keyword(s):  
Fault Detection ◽  
Performance Indicator ◽  
High Energy ◽  
Hvac Systems ◽  
Coefficient Of Performance ◽  
Total Power ◽  
Hvac System ◽  
Total Power Consumption ◽  
Detailed Simulation ◽  
Performance Distribution

Detecting and diagnosing faults that degrade the performance of heating, ventilation, and air conditioning (HVAC) systems is very important for maintaining high energy efficiency. The performance of HVAC systems can be evaluated by analyzing monitored data. However, data from a HVAC system generally includes uncertainties, which renders monitored data less reliable. Then, we focused on uncertainties and a calculated performance distribution. The uncertainties from sensors, actuators, and communications were modelled stochastically and were incorporated into a detailed simulation. The system coefficient of performance (SCOP) was used as a performance indicator, which is defined as the ratio of suppled heat to total power consumption. The SCOP distributions over the course of representative weeks in 2007 and 2015 were calculated by repeating the simulation 2,000 times with different uncertainties. Regarding the results for 2015, the 90% confidence interval of the distribution was -4.9% to 5.8% from the SCOP value without uncertainties. The SCOP value determined from the monitored data in 2015 was outside of the low end of the distribution though that in 2007 was inside of the interval. Through an analysis of the monitored data, it was found that fault detection is possible by comparing the monitored data with the distribution.

A SAT-Based Methodology for Effective Clock Gating for Power Minimization

2018 ◽  
Vol 28 (01) ◽  
pp. 1950011
Author(s):  
Khushbu Chandrakar ◽  
Suchismita Roy
Keyword(s):  
Power Consumption ◽  
Optimization Techniques ◽  
Total Power ◽  
Clock Signal ◽  
Clock Gating ◽  
Clock Tree ◽  
Synchronous Circuits ◽  
Design And Optimization ◽  
Total Power Consumption ◽  
On Chip

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

Optimal Fan Speed Control for Thermal Management of Servers

2009 ◽  
Author(s):  
Zhikui Wang ◽  
Cullen Bash ◽  
Niraj Tolia ◽  
Manish Marwah ◽  
Xiaoyun Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
First Principles ◽  
Hot Spot ◽  
Speed Control ◽  
Total Power ◽  
Essential Requirement ◽  
Total Power Consumption ◽  
Fan Speed ◽  
Cooling Air

Improving the cooling efficiency of servers has become an essential requirement in data centers today as the power used to cool the servers has become an increasingly large component of the total power consumption. Additionally, fan speed control has emerged in recent years as a critical part of system thermal architecture. However, the state of the art in server fan control often results in over provisioning of air flow that leads to high fan power consumption. It can be exacerbated in server architectures that share cooling resources among server components, where single hot spot can often drive the operation of a multiplicity of fans. To address this problem, this paper presents a novel multi-input multi-output (MIMO) fan controller that utilizes thermal models developed from first-principles to manipulate the operation of fans. The controller tunes the speeds of individual fans proactively based on prediction of the sever temperatures. Experimental results show that, with fans controlled by the optimal controller, over-provisioning of cooling air is eliminated, temperatures are more tightly controlled and fan energy consumption is reduced by up to 20% compared to that with a zone-based feedback controller.

scholarly journals Analysis and Design of Colpitts Oscillator for Short-range WSN

2016 ◽  
Vol 62 (3) ◽  
pp. 279-282
Author(s):  
Mousa Yousefi
Keyword(s):  
Energy Efficiency ◽  
Output Power ◽  
Short Range ◽  
Cmos Technology ◽  
Paper Analysis ◽  
Total Power ◽  
Colpitts Oscillator ◽  
Analysis And Design ◽  
Total Power Consumption ◽  
On Chip

Abstract In this paper, analysis and design of colpitts oscillator with ability to transmit data at low output power with application in short-range wireless sensor networks such as MICS is described. Reducing the area required to implement the transmitter, on-chip implementation and appropriate energy efficiency are the advantages of this structure that makes it suitable for the design of short-range transmitter in biomedical applications. The proposed OOK transmitter works at 405 MHz with 10 Mbps data rate. Output power and total power consumption are 25 µW and 726 µW, respectively. Energy efficiency is 72.6 pJ/bit. The transmitter has been designed and simulated in 0.18 µm CMOS technology.

Analysis of Refrigeration Requirements of Digital Processors in Subambient Temperatures

2010 ◽  
Vol 7 (4) ◽  
pp. 197-204 ◽  
Author(s):  
Won Ho Park ◽  
Tamer Ali ◽  
C. K. Ken Yang
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Power Reduction ◽  
Coefficient Of Performance ◽  
System Level ◽  
Total Power ◽  
Optimized Design ◽  
Total Power Consumption ◽  
Level Model ◽  
Viable Approach

The total power consumption for high-performance computing systems is a serious concern for designers of integrated circuits and systems. It is well known that cooling the operating temperature results in reduced electronic power and/or speed gains. However, total power dissipation includes both electronic power and the refrigeration power. This study explores the optimal operating temperatures and the amount of total power reduction at subambient temperatures. This paper presents a realistic system-level model that includes both the electronic and the refrigeration systems. Analysis using the model shows the optimal temperature, and sensitivity to parameters of the electronic and refrigeration systems. For instance, a system with 50% electronic leakage and a minimum refrigeration coefficient of performance (COP) of 3.3, the optimized design operates at 8°C and offers a 44% power reduction over the noncooled design. Analysis also shows that temperatures near that of domestic freezers is nearly optimal for digital processors and such cooling may be viable approach for current and future electronics due to the scaling trends of integrated circuits technology.

Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects

2020 ◽  
Vol 29 (12) ◽  
pp. 2050185 ◽  
Author(s):  
Himanshu Sharma ◽  
Karmjit Singh Sandha
Keyword(s):  
Integrated Circuit ◽  
Fermi Energy ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Layer Graphene ◽  
Parasitic Parameters ◽  
On Chip ◽  
Power Delay Product ◽  
Technology Nodes ◽  
The Impact

Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

scholarly journals 14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

2021 ◽  
Vol 2021 ◽  
pp. 1-17
Author(s):  
Xiaowei Zhang ◽  
Wei Fan ◽  
Jianxiong Xi ◽  
Lenian He
Keyword(s):  
Sampling Rate ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Fully Differential ◽  
Total Power Consumption ◽  
The Impact

This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three-way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024 , and the pixel pitch is 12.5   μ m × 12.5   μ m . The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38  mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 V PP differential input signal and the total power consumption of the CIS is about 613 mW.

scholarly journals Power Optimization for ASIC Design (Low power ASIC)

2014 ◽  
pp. 258-265
Author(s):  
Hitesh H Vandra
Keyword(s):  
Power Systems ◽  
Embedded System ◽  
Low Power ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Optimization Techniques ◽  
Total Power ◽  
Asic Design ◽  
Switching Power ◽  
Total Power Consumption

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce feature size. Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. However, questions regarding the limits of scaling have arisen in recent years due to the presence of leakage. As the supply voltage is lowered to satisfy the performance requirement, the threshold voltage has to be scaled, which increases leakage. More than 40% of the total power consumption is due to leakage of the transistor is in DSM. This leakage will increase with scaling become comparable with switching power. The goal of this paper is to analyse different low power circuits and optimization techniques to improve the power dissipation with the use of power gating components, retention registers, level shifters, isolation cells etc.

Sign in / Sign up

Export Citation Format

Share Document