Analysis of Refrigeration Requirements of Digital Processors in Subambient Temperatures

2010 ◽  
Vol 7 (4) ◽  
pp. 197-204 ◽  
Author(s):  
Won Ho Park ◽  
Tamer Ali ◽  
C. K. Ken Yang
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Power Reduction ◽  
Coefficient Of Performance ◽  
System Level ◽  
Total Power ◽  
Optimized Design ◽  
Total Power Consumption ◽  
Level Model ◽  
Viable Approach

The total power consumption for high-performance computing systems is a serious concern for designers of integrated circuits and systems. It is well known that cooling the operating temperature results in reduced electronic power and/or speed gains. However, total power dissipation includes both electronic power and the refrigeration power. This study explores the optimal operating temperatures and the amount of total power reduction at subambient temperatures. This paper presents a realistic system-level model that includes both the electronic and the refrigeration systems. Analysis using the model shows the optimal temperature, and sensitivity to parameters of the electronic and refrigeration systems. For instance, a system with 50% electronic leakage and a minimum refrigeration coefficient of performance (COP) of 3.3, the optimized design operates at 8°C and offers a 44% power reduction over the noncooled design. Analysis also shows that temperatures near that of domestic freezers is nearly optimal for digital processors and such cooling may be viable approach for current and future electronics due to the scaling trends of integrated circuits technology.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Fault detection in HVAC systems using a distribution considering uncertainties

2019 ◽  
Vol 111 ◽  
pp. 05010
Author(s):  
Shohei Miyata ◽  
Yasunori Akashi ◽  
Jongyeon Lim ◽  
Yasuhiro Kuwahara
Keyword(s):  
Fault Detection ◽  
Performance Indicator ◽  
High Energy ◽  
Hvac Systems ◽  
Coefficient Of Performance ◽  
Total Power ◽  
Hvac System ◽  
Total Power Consumption ◽  
Detailed Simulation ◽  
Performance Distribution

Detecting and diagnosing faults that degrade the performance of heating, ventilation, and air conditioning (HVAC) systems is very important for maintaining high energy efficiency. The performance of HVAC systems can be evaluated by analyzing monitored data. However, data from a HVAC system generally includes uncertainties, which renders monitored data less reliable. Then, we focused on uncertainties and a calculated performance distribution. The uncertainties from sensors, actuators, and communications were modelled stochastically and were incorporated into a detailed simulation. The system coefficient of performance (SCOP) was used as a performance indicator, which is defined as the ratio of suppled heat to total power consumption. The SCOP distributions over the course of representative weeks in 2007 and 2015 were calculated by repeating the simulation 2,000 times with different uncertainties. Regarding the results for 2015, the 90% confidence interval of the distribution was -4.9% to 5.8% from the SCOP value without uncertainties. The SCOP value determined from the monitored data in 2015 was outside of the low end of the distribution though that in 2007 was inside of the interval. Through an analysis of the monitored data, it was found that fault detection is possible by comparing the monitored data with the distribution.

System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices

2007 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
System Level ◽  
Total Power ◽  
Main Concern ◽  
Optimized Design ◽  
Passive Components ◽  
Thermal Budget ◽  
The Impact

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.

scholarly journals A Highly Linear Low-Noise Transimpedance Amplifier for Indoor Fiber-Wireless Remote Antenna Units

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 437 ◽  
Author(s):  
Guillermo Royo ◽  
Antonio D. Martinez-Perez ◽  
Carlos Sanchez-Azqueta ◽  
Concepcion Aldea ◽  
Santiago Celma
Keyword(s):  
Cmos Technology ◽  
Antenna System ◽  
Open Loop ◽  
Low Noise ◽  
Total Power ◽  
Transimpedance Amplifier ◽  
Optimized Design ◽  
Error Vector Magnitude ◽  
Digitally Programmable ◽  
Total Power Consumption

This article presents an optimized design of a low-noise transimpedance amplifier (TIA) with high linearity for use in the downlink receiver of a remote antenna unit (RAU). The aim of this design is to be used in a cost-effective indoor distributed antenna system (DAS) for WLAN transmission using a mixed fiber-wireless system. The circuit topology consists of a fully differential shunt–shunt feedback TIA with digitally programmable transimpedance. An open-loop gain compensation technique is used to maintain stability and constant bandwidth (BW). The TIA has been fabricated in 65 nm CMOS technology with a 1.2 V voltage supply. The total power consumption of the TIA is 6 mW. A complete electrical and optical characterization with a 1550 nm PIN photodiode has been performed to demonstrate the reliable 54 Mb/s 802.11a WLAN transmission achieved with an error vector magnitude (EVM) lower than 3% for a 20 dB optical input range.

Power Reduction Techniques in Cloud Data Centers

2014 ◽  
Vol 1061-1062 ◽  
pp. 1070-1073
Author(s):  
Lei Tang ◽  
Zheng Ce Cai ◽  
Guo Long Chen ◽  
Xian Wei Li
Keyword(s):  
Cloud Computing ◽  
Data Centers ◽  
Large Fraction ◽  
Power Reduction ◽  
Cloud Services ◽  
Total Power ◽  
Cloud Data ◽  
Reduction Techniques ◽  
Total Power Consumption ◽  
Cloud Data Centers

In recent years, cloud computing has received much attention from both academia and engineering areas. With more and more companies beginning to provide cloud services, more and more data centers are being built. Recent studies show that the energy consumed by cloud data centers accounts for a large fraction of the total power consumption today. This motivates us to survey power reduction techniques in cloud data centers.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

scholarly journals A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter

2021 ◽  
Vol 11 (2) ◽  
pp. 15
Author(s):  
Marcello De Matteis ◽  
Federico Fary ◽  
Elia A. Vallicelli ◽  
Andrea Baschirotto
Keyword(s):  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Noise Power ◽  
Analog Filter ◽  
Figures Of Merit ◽  
Total Power Consumption ◽  
Source Follower ◽  
Order Continuous ◽  
28 Nm

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

scholarly journals Modified Keeper Controlled Domino Circuit for Low Power High Performance Wide Fan in OR Gates

2019 ◽  
Vol 8 (6) ◽  
pp. 3121-3126
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Total Power ◽  
Total Power Consumption ◽  
Power Models ◽  
Domino Circuit ◽  
Circuit Techniques ◽  
Capacitive Loading ◽  
Technology Nodes

A novel modified keeper technique has been proposed in this paper for domino logic circuits implemented as wide fan in OR gate. Few circuit parameters as capacitivie loading and delay are major concerns for OR gates in deeper technology nodes. This design focuses on a comparator block with modified dual keeperto maintain the output logic state. Additionally it comprises of a delay loop to limit the contention current. The proposed design reduces the input capacitive loading and total power consumption by the circuit, while keeping the speed of operation same. It was compared with latest domino circuit techniques and the proposed design MKCD has achieved a reduction of 41% in power consumption in 64 bit configuration as compared to conventional domino circuit SFLD. Average noise immunity has also increased by more than twice as compared to SFLD. The simulations were performed using 90nm PTM low power models.

scholarly journals High Performance Bulk Driven Operational Trans Conductance Amplifier and Applications

2019 ◽  
Vol 8 (12S) ◽  
pp. 344-347
Keyword(s):  
Power Supply ◽  
Output Voltage ◽  
High Performance ◽  
Cmos Technology ◽  
Total Power ◽  
Operational Transconductance Amplifier ◽  
Weak Inversion ◽  
Input And Output ◽  
Transconductance Amplifier ◽  
Total Power Consumption

In this paper a bulk driven Fully cascoded operational transconductance amplifier(FCOTA) is designed. OTA applications are designed for voltage controlled current amplifier, filters and analog subtractor. With the current sizing method, all transistors in FCOTA work under weak inversion field. The total current in the proposed amplifier in terms of nano amperes only. As part of low power the circuit operated with the power supply of 0.8V. The main important features of the design are good linearity and accuracy. Full input and output voltage swings. This circuit has been constructed using CMOS technology with UMC90 nm. The circuit’s total power consumption is 620nW

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