scholarly journals 14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

2021 ◽  
Vol 2021 ◽  
pp. 1-17
Author(s):  
Xiaowei Zhang ◽  
Wei Fan ◽  
Jianxiong Xi ◽  
Lenian He
Keyword(s):  
Sampling Rate ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Fully Differential ◽  
Total Power Consumption ◽  
The Impact

This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three-way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024 , and the pixel pitch is 12.5   μ m × 12.5   μ m . The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38  mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 V PP differential input signal and the total power consumption of the CIS is about 613 mW.

A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Total Power ◽  
Cmos Process ◽  
Current Amplifier ◽  
X Ray ◽  
Total Power Consumption ◽  
Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

scholarly journals A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 590
Author(s):  
Nishat Tarannum Tasneem ◽  
Ifana Mahbub
Keyword(s):  
Sampling Rate ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Noise Power ◽  
Neural Signal ◽  
Total Power Consumption ◽  
Signal Recording ◽  
Neural Signal Recording

This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

scholarly journals On-CMOS Image Sensor Processing for Lane Detection

Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3713
Author(s):  
Soyeon Lee ◽  
Bohyeok Jeong ◽  
Keunyeol Park ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Edge Detection ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Image Resolution ◽  
Lane Detection ◽  
Frame Rate ◽  
Total Power ◽  
Detection Accuracy ◽  
Total Power Consumption

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

scholarly journals Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2031
Author(s):  
Konstantin D. Stefanov ◽  
Martin J. Prest ◽  
Mark Downing ◽  
Elizabeth George ◽  
Naidu Bezawada ◽  
...  
Keyword(s):  
Single Photon ◽  
Sampling Rate ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Single Photons ◽  
Noise Performance ◽  
The Impact ◽  
Non Destructive ◽  
Multiple Charge ◽  
Pinned Photodiode

A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging, the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor process. Using simulations, the noise performance of the pixel was determined as a function of the number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths and limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected performance of our first prototype device indicates that single-photon imaging is within reach and could enable ground-breaking performances in many scientific and industrial imaging applications.

scholarly journals A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 743
Author(s):  
Zunkai Huang ◽  
Jinglin Huang ◽  
Li Tian ◽  
Ning Wang ◽  
Yongxin Zhu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Single Photon ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Digital Converter ◽  
Delay Element ◽  
Time To Digital Converter ◽  
Total Power Consumption

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

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