System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices

2007 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
System Level ◽  
Total Power ◽  
Main Concern ◽  
Optimized Design ◽  
Passive Components ◽  
Thermal Budget ◽  
The Impact

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.

System Level Thermal Evaluation and Optimization of an Automotive Module Incorporating Several Power Packages

2005 ◽  
Author(s):  
Victor Chiriac ◽  
Tom Lee ◽  
Kim Gauen
Keyword(s):  
Ambient Temperature ◽  
Thermal Performance ◽  
Heat Dissipation ◽  
Daily Basis ◽  
System Level ◽  
Main Concern ◽  
Transfer Coefficients ◽  
Passive Components ◽  
Reference Design ◽  
System Module

The conjugate thermal performance of a microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC packaging incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance. The main concern is the possibility of exceeding the thermal budget for the large system incorporating seven power packages with additional sources of heat dissipation in an enclosure, at an external ambient temperature of 85°C. The overall thermal impact of the metal trace dissipation, header heating and other passive components under various powered conditions is evaluated. An additional revised model includes additional passive components (32 LD SOIC and QFN packages) on the PCB, a modified harness extending ∼ 30.4 cm outside the enclosure, and additional heating in the connectors. Several additional cases are investigated, varying the heat transfer coefficients outside the enclosure, at an ambient temperature of 85°C. The peak temperatures range from 121.4°C to 126.4°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 11.03°C/W to 12.5°C/W. The optimized numerical model approximates closely the empirical results (121–126°C vs. 127.5°C), within 1–2%.

Thermal Performance Evaluation and Economic Analysis of LED Integrated with Thermoelectric Cooler Package

2011 ◽  
Vol 216 ◽  
pp. 106-110 ◽  
Author(s):  
Hong Qin ◽  
Da Liang Zhong ◽  
Chang Hong Wang
Keyword(s):  
Economic Analysis ◽  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
Light Emitting Diode ◽  
Vital Role ◽  
Junction Temperature ◽  
Total Power ◽  
Thermoelectric Cooler ◽  
Light Emitting

Thermal management is an important issue for light emitting diodes’ utilization. For high power light emitting diode (LED), active heat dissipation method plays a vital role. As a new cooling device, thermoelectric cooler (TEC) is applied in LED packaging for the precisely temperature controlled advantage. In order to evaluate the thermal performance of the TEC packaging designs in LED, experimental measurement is used to assess the chip’s junction temperature of three different cooling models, which include the heatsink model, the heatsink and fan model and the TEC, heatsink and fan model. Based on the research, it is better to apply TEC cooling methods with the power dissipation of LED less than 35 W and the wind speed is 3.6 m/s. However, the power dissipation of TEC itself plays a vital role of the total power dissipation of LED packaging. The results of economic analysis shows that the LED integrated with TEC package achieves 22.34% and 44.73% electric energy saving under the condition of 20 W and 30 W power dissipation of the LED chip contrasts to the fluorescent lamp, but sacrifices 2.71% electric power under the condition of 10 W power dissipation of the LED chip.

System Level Thermal Performance Evaluation of New Inverted Exposed Pad Packages for Automotive Applications

2006 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Automotive Applications ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel 54 lead SOIC (with inverted exposed Cu pad) packages for automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rjhs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, a comparison with a different exposed pad package is made. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package. Several cases are evaluated in the paper, with an emphasis on the superior thermal performance of new packages for automotive applications.

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001635-001655
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Worst Case ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.

System-Level Transient Thermal Analysis for Performance Optimization of High Power Microelectronics

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
H. S. Chen
Keyword(s):  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Optimal Operation ◽  
System Level ◽  
Main Concern ◽  
Efficient Operation ◽  
Normal Test ◽  
Transient Thermal ◽  
Short Time

The increasing trend in power levels and densities leads to the need of design thermal optimization, at either module or system level. A numerical study using finite-volume software was conducted to model the transient thermal behavior of a system including a package dissipating large amounts of power over short time durations. The system is evaluated by choosing the appropriate heat sink for the efficient operation of the device under 100W of constant powering, also to enhance the thermal performance of the enclosure/box containing the test stack-up. The intent of the study is to provide a meaningful understanding and prediction of the high transient powering scenarios. The study focuses on several powering and system design scenarios, identifying the main issues encountered during a normal device operation. The power source dissipates 100W for 2 seconds then is cooled for another 2 seconds. This thermal cycle is likely to occur several times during a normal test-up, and it is the main concern of the manufacturers not to exceed a limit temperature during the device testing operation. The transient trend is further extrapolated analytically to extract the steady state peak temperature values, in order to maintain the device peak temperatures below 120°C. The benefit of the study is related to the possibility to extract the maximum/minimum temperatures for a real test involving a large number of heating-cooling cycles, yet maintaining the initial and peak temperatures within a certain range, for the optimal operation of the device. The flow and heat transfer fields are thoroughly investigated. By using a combination of numerical and analytical study, the thermal performance of the device undergoing infinity of periodic thermal cycles is further predicted.

scholarly journals Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1930
Author(s):  
Azwad Tamir ◽  
Milad Salem ◽  
Jie Lin ◽  
Qutaiba Alasad ◽  
Jiann-shiun Yuan
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
3D Design ◽  
3D Ic ◽  
3D Ics ◽  
Custom Made ◽  
Partitioning Algorithms ◽  
Automation Tools ◽  
The Impact ◽  
Place And Route

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

Thermal Management for High Power Light-Emitting Diode Street Lamp

2010 ◽  
Author(s):  
M. Ying ◽  
S. M. L. Nai ◽  
P. Shi ◽  
J. Wei ◽  
C. K. Cheng ◽  
...  
Keyword(s):  
Thermal Management ◽  
Thermal Performance ◽  
High Power ◽  
Heat Dissipation ◽  
Light Emitting Diode ◽  
System Level ◽  
Light Emitting ◽  
High Power Led ◽  
Street Lamp ◽  
Lamp System

Light-emitting diode (LED) street lamp has gained its acceptance rapidly in the lighting system as one of choices for low power consumption, high reliability, dimmability, high operation hours, and good color rendering applications. However, as the LED chip temperature strongly affects the optical extraction and the reliability of the LED lamps, LED street lamp performance is heavily relied on a successful thermal management, especially when applications require LED street lamp to operate at high power and hash environment to obtain the desired brightness. As such, a well-designed thermal management, which can lower the LED chip operation temperature, becomes one of the necessities when developing LED street lamp system. The current study developed an effective heat dissipation method for the high power LED street lamp with the consideration of design for manufacturability. Different manufacturable structure designs were proposed for the high power street lamp. The thermal contact conductance between aluminum interfaces was measured in order to provide the system assembly guidelines. The module level thermal performance was also investigated with thermocouples. In addition, finite element (FE) models were established for the temperature simulation of both the module and lamp system. The coefficient of natural convection of the heat sink surface was determined by the correlation of the measurement and simulation results. The system level FE model was employed to optimize and verify the heat dissipation concepts numerically. An optimized structure design and prototype has shown that the high power LED street lamp system can meet the thermal performance requirements.

Analysis of Refrigeration Requirements of Digital Processors in Subambient Temperatures

2010 ◽  
Vol 7 (4) ◽  
pp. 197-204 ◽  
Author(s):  
Won Ho Park ◽  
Tamer Ali ◽  
C. K. Ken Yang
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Power Reduction ◽  
Coefficient Of Performance ◽  
System Level ◽  
Total Power ◽  
Optimized Design ◽  
Total Power Consumption ◽  
Level Model ◽  
Viable Approach

The total power consumption for high-performance computing systems is a serious concern for designers of integrated circuits and systems. It is well known that cooling the operating temperature results in reduced electronic power and/or speed gains. However, total power dissipation includes both electronic power and the refrigeration power. This study explores the optimal operating temperatures and the amount of total power reduction at subambient temperatures. This paper presents a realistic system-level model that includes both the electronic and the refrigeration systems. Analysis using the model shows the optimal temperature, and sensitivity to parameters of the electronic and refrigeration systems. For instance, a system with 50% electronic leakage and a minimum refrigeration coefficient of performance (COP) of 3.3, the optimized design operates at 8°C and offers a 44% power reduction over the noncooled design. Analysis also shows that temperatures near that of domestic freezers is nearly optimal for digital processors and such cooling may be viable approach for current and future electronics due to the scaling trends of integrated circuits technology.

Steady-State and Transient Thermal Performance Optimization of Power Automotive Modules

2009 ◽  
Author(s):  
Victor Chiriac
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
System Level ◽  
Main Concern ◽  
Thermal Impact ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Transient Thermal

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of power packages for automotive applications. The automotive industry deals on a daily basis with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of IC incorporation into a system module, for present and future product development. Several packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal impact of the thicker lead frame and die attach material on the overall thermal behavior is evaluated. The main concern is exceeding the thermal budget at an external ambient temperature of 85°C, specific for the relatively extreme automotive operating environments. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ∼106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ∼260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. When the isothermal boundary is attached to package bottom, peak temperature drops by 20% after 40 ms. Additional system level with multiple optimized packages placed on a custom PCB is evaluated numerically and experimentally, placing an emphasis on the superior thermal performance of this new class of power packages for automotive applications. The optimized numerical model approximates closely the empirical results (121–126°C vs. 127.5°C), within 1–2%.

Thermal Management of Voids and Delamination in TIMs

2005 ◽  
Author(s):  
Vadim Gektin
Keyword(s):  
Experimental Data ◽  
Thermal Conductivity ◽  
Performance Analysis ◽  
Effective Thermal Conductivity ◽  
Thermal Management ◽  
Thermal Performance ◽  
Power Dissipation ◽  
Thermal Measurements ◽  
The Impact ◽  
The Relationship

The paper parametrically assesses the impact of the voids/delamination on the system thermal performance. Analysis are carried out numerically and validated against experimental data (thermal measurements and C-SAM images). Topics covered include the relationship between voids/delamination and TIMs’ and heat spreader’s effective thermal conductivity; sensitivity of the system thermal performance to void/delamination size and location; voids/delamination impact vs. on the chip power dissipation (uniform vs. non-uniform); comparison of TIM1 vs. TIM2 voids impact; and, finally, comparison of voids vs. delamination.

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