Solder Joint Reliability Challenges in Sub 1.00 mm Ball Pitch for Flip Chip Ball Grid Array

Author(s):  
Keh Shin Beh ◽  
Wei Keat Loh ◽  
Jenn Seong Leong ◽  
Wooi Aun Tan

FCBGA is an electronic package used to achieve a high Inputs/Outputs (I/Os). To continue to achieve a higher I/O count without increasing package size, ball pitch reduction is inevitable. However, ball pitch reduction using smaller ball size has posed substantial challenges to solder joint reliability (SJR). On top of that, rising power dissipation requirement in FCBGA package has created a need for high performance heat sinks. These heat sinks require significant compression loading to ensure good thermal conductance of thermal interface materials. The impact of these loads on SJR has typically not been considered in thermal cycle stressing. Hence, this paper focuses on different types of heat sinks and their compressive load effect on solder joint thermal fatigue performance. It also covers package size and board thickness effect when heat sink compressive load is taken into account during thermal stressing. Lastly, lead free and eutectic solders at sub 1.00mm ball pitch technology were also evaluated.

Author(s):  
Frank Z. Liang ◽  
Rick L. Williams

As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer’s critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models.


2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung

Author(s):  
Jefferson Talledo

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.


Sign in / Sign up

Export Citation Format

Share Document