Application of a Novel Flip Chip Solder Joint Inspection System to Chips on an FR-4 Substrate

2000 ◽  
Author(s):  
Dathan S. Erdahl ◽  
Sheng Liu ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Bump ◽  
Solder Joints ◽  
Inspection System ◽  
Vibration Displacement ◽  
Manufacturing Defects ◽  
Flip Chips ◽  
Solder Joint Inspection

Abstract Because the trend in electronic interconnection technology is toward the development of solder bump technologies, that include flip chips, chip scale packages, multi-chip modules (MCMs), and ball grid array (BGA) packages, solder bump inspection methods must be developed to allow rapid, accurate, and high resolution on-line inspection of joint quality. Although traditional methods can detect some manufacturing defects, they do not actually test the mechanical quality of the connection. A novel solder-joint inspection system has been developed based on laser ultrasound and interferometric techniques. A pulsed laser generates ultrasound on the chip’s surface and the whole chip is excited into vibration modes. An interferometer is used to measure the vibration displacement of the chip’s surface. Solder joints with different qualities cause different vibration responses, acting as constraints on the system. The system was used to inspect the quality of solder joints on a group of flip chips mounted on FR-4 substrates, and the results show the ability of the system to detect defects such as missing solder balls, cracked chips, and gross misalignment.

The size effect on intermetallic microstructure evolution of critical solder joints for flip chip assemblies

2015 ◽  
Vol 27 (4) ◽  
pp. 178-184 ◽  
Author(s):  
Ye Tian ◽  
Justin Chow ◽  
Xi Liu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Design Methodology ◽  
Growth Process ◽  
Flip Chip ◽  
Solder Bump ◽  
Solder Joints ◽  
Solder Matrix ◽  
Industrial Practice ◽  
Content Type ◽  
Flip Chips

Purpose – The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix. Design/methodology/approach – This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies. Findings – After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process. Originality/value – With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

scholarly journals Prediction of mechanical properties and fatigue life of nano silver paste in chip interconnection

2020 ◽  
Author(s):  
Hui YANG ◽  
Jihui Wu
Keyword(s):  
Fatigue Life ◽  
Solder Joint ◽  
Thermal Cycling ◽  
Solder Joints ◽  
Stress And Strain ◽  
Nano Silver ◽  
Finite Element Software ◽  
Flip Chips ◽  
Empirical Correction ◽  
Prediction Of Mechanical Properties

Abstract The simulation of nano-silver solder joints in flip-chips is performed by the finite element software ANSYS, and the stress-strain distribution results of the solder joints are displayed. In this simulation, the solder joints use Anand viscoplastic constitutive model, which can reasonably simulate the stress and strain of solder joints under thermal cycling load. At the same time this model has been embedded in ANSYS software, so it is more convenient to use. The final simulation results show that the areas where the maximum stresses and strains occur at the solder joints are mostly distributed in the contact areas between the solder joints and the copper pillars and at the solder joints. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. Based on comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of nano-silver solder joints. The analysis results provide a reference for the application of nano-silver solder in the electronic packaging industry.

Vibration Analysis Based Modeling and Defect Recognition for Flip Chip Solder Joint Inspection

2000 ◽  
Author(s):  
Sheng Liu ◽  
Dathan Erdahl ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Vibration Analysis ◽  
Flip Chip ◽  
Process Development ◽  
Great Promise ◽  
Quality Inspection ◽  
Vibration Frequencies ◽  
Vibration Responses ◽  
Solder Joint Inspection ◽  
Joint Quality

Abstract A novel approach for flip chip solder joint quality inspection based on vibration analysis is presented. Traditional solder joint inspection methods have their limitations when applied to flip chip solder joint quality inspection. The vibration detection method is a new approach which has advantages such as being non-contact, non-destructive, fast and can be used on-line or during process development. In this technique, a flip chip was modeled as a thick plate supported by solder bumps. Changes in solder joint quality produce different vibration responses of flip chip, and change its natural vibration frequencies. In this paper, the vibration frequencies of a flip chip on a ceramic substrate were calculated using the finite element method. Based on vibration analysis, a laser ultrasound and interferometric system was developed for flip chip solder joint quality inspection. In this system, chips with good solder joints can be distinguished from chips with bad joints using their vibration responses and frequencies. Defects recognition methods were developed and tested. Results indicate this approach offers great promise for solder bump inspection in flip chip, BGA and chip scale packages.

Use of Wafer Applied Underfill for 3D Stacking

2011 ◽  
Vol 2011 (1) ◽  
pp. 000008-000016 ◽  
Author(s):  
Antonio La Manna ◽  
K. J. Rebibis ◽  
C. Gerets ◽  
E. Beyne
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Initial Assessment ◽  
Test Vehicle ◽  
Differential Movement ◽  
The Right ◽  
3D Stacking ◽  
Material Uniformity ◽  
Work Done

A key element for improving 3D stacking reliability is the choice of the right Underfill materials. The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

Reliability of Underfill-Encapsulated Flip-Chips With Heat Spreaders

1998 ◽  
Vol 120 (4) ◽  
pp. 322-327 ◽  
Author(s):  
H. Doi ◽  
K. Kawano ◽  
A. Yasukawa ◽  
T. Sato
Keyword(s):  
Mechanical Properties ◽  
Fatigue Life ◽  
Thermal Cycling ◽  
Failure Mode ◽  
Flip Chip ◽  
Solder Joints ◽  
Alumina Substrate ◽  
Heat Spreader ◽  
Flip Chips ◽  
Heat Spreaders

The effect of a heat spreader on the life of the solder joints for underfill-encapsulated, flip-chip packages is investigated through stress analyses and thermal cycling tests. An underfill with suitable mechanical properties is found to be able to prolong the fatigue life of the solder joints even in a package with a heat spreader and an alumina substrate. The delamination of the underfill from the chip is revealed as another critical failure mode for which the shape of the underfill fillet has a large effect.

Detection of Solder Bump Defects in Electronic Packages Using Local Temporal Coherence Analysis of Laser Ultrasonic Signals

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Jin Yang ◽  
I. Charles Ume
Keyword(s):  
Solder Bump ◽  
Temporal Coherence ◽  
Acoustic Microscopy ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Electronic Packages ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Inspection

Microelectronics packaging technology has evolved from through-hole and bulk configurations to surface-mount and small-profile configurations. Surface mount devices, such as flip chip packages, chip scale packages, and ball grid arrays, use solder bump interconnections between them and substrates/printed wiring boards. Solder bumps, which are hidden between the device and the substrate/board, are difficult to inspect. A solder bump inspection system was developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder joint/bump defects, including missing, misaligned, open, and cracked solder joints/bumps in flip chips, chip scale packages, and multilayer ceramic capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using the interferometric technique. This paper presents a local temporal coherence (LTC) analysis of laser ultrasound signals and compares it to previous signal-processing methods, including error ratio and correlation coefficient methods. The results showed that LTC analysis increased measurement accuracy and sensitivity for inspecting solder bump defects in electronic packages. Laser ultrasound inspection results are also compared with X-ray and C-mode scanning acoustic microscopy results. In particular, this paper discusses defect detection for 6.35×6.35×0.6 mm3 flip chips and flip chips (“SiMAF;” Siemens AG) with lead-free solder bumps.

Failure Mechanism of Electromigration in Solder Joint

2008 ◽  
Vol 44-46 ◽  
pp. 905-910 ◽  
Author(s):  
Yu Dong Lu ◽  
Xiao Qi He ◽  
Yun Fei En ◽  
Xin Wang
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Joints ◽  
High Current Density ◽  
Electron Flow ◽  
Design Rule ◽  
Bottom Surface ◽  
Constant Density ◽  
Linear Change ◽  
Void Migration

In advanced electronic products, electromigration-induced failure is one of the most serious problems in fine pitch flip chip solder joints because the design rule in devices requires high current density through small solder joints for high performance and miniaturization. The failure mode induced by electromigration in the flip chip solder joint is unique, owing to the loss of under bump metallurgy (UBM) and the interfacial void formation at the cathode contact interface. In this study, Electromigration of flip chip solder joints has been investigated under a constant density of 2.45×104 A/cm2 at 120 °C. The in-situ marker displacements during the electromigration test was measured and found to show a rough linear change as a function of time. Scanning electron microscopic images of the cross section of samples showed the existence of voids at the interface between Al interconnection and under bump metallurgy. The void movement was matched with the marker displacements during the electromigration test, and voids moved to the cathode interface between Al interconnection and under bump metallurgy in the downward electron flow (from chip to substrate) joint. The mechanism of electromigration-induced void migration and failure in the flip chip are discussed. During electromigration, a flux of atoms is driven from the cathode to the anode or a flux of vacancies in the opposite direction. It can lead to two possible mechanisms of void migration. First, if we regard the void as a rigid marker of diffusion, it will be displaced towards the cathode by the atomic flux in the electromigration, Second, if we consider surface diffusion on the void surface, electromigration will drive atoms on the top surface of the void to the bottom surface of the void, and consequently the void will move towards the cathode.

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