Detection of Solder Bump Defects in Electronic Packages Using Local Temporal Coherence Analysis of Laser Ultrasonic Signals

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Jin Yang ◽  
I. Charles Ume
Keyword(s):  
Solder Bump ◽  
Temporal Coherence ◽  
Acoustic Microscopy ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Electronic Packages ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Inspection

Microelectronics packaging technology has evolved from through-hole and bulk configurations to surface-mount and small-profile configurations. Surface mount devices, such as flip chip packages, chip scale packages, and ball grid arrays, use solder bump interconnections between them and substrates/printed wiring boards. Solder bumps, which are hidden between the device and the substrate/board, are difficult to inspect. A solder bump inspection system was developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder joint/bump defects, including missing, misaligned, open, and cracked solder joints/bumps in flip chips, chip scale packages, and multilayer ceramic capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using the interferometric technique. This paper presents a local temporal coherence (LTC) analysis of laser ultrasound signals and compares it to previous signal-processing methods, including error ratio and correlation coefficient methods. The results showed that LTC analysis increased measurement accuracy and sensitivity for inspecting solder bump defects in electronic packages. Laser ultrasound inspection results are also compared with X-ray and C-mode scanning acoustic microscopy results. In particular, this paper discusses defect detection for 6.35×6.35×0.6 mm3 flip chips and flip chips (“SiMAF;” Siemens AG) with lead-free solder bumps.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Quality Evaluation of Solder Bump in PBGA Package for Commercial Product Application Using Laser Ultrasonic Technique

2013 ◽  
Author(s):  
Jie Gong ◽  
I. Charles Ume ◽  
Kola Akinade ◽  
Amiya Ray Chaudhuri
Keyword(s):  
Solder Bump ◽  
Commercial Product ◽  
Test Results ◽  
Flip Chips ◽  
Solder Bumps ◽  
Plastic Ball ◽  
Out Of Plane ◽  
Ultrasound Inspection ◽  
Plane Displacement

A laser-ultrasound inspection (LUI) system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, land grid array packages and chip capacitors. This system uses a pulsed laser to induce ultrasound in the chip packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using a laser interferometer. The amplitudes of the out-of-plane displacement are usually in the order of nanometer. The quality of solder bumps is evaluated by analyzing the transient responses. In this paper, this system is used to evaluate quality of solder bumps in plastic ball grid array (PBGA) package on a commercial product. Each chip was divided into 4 quadrants during testing and signal processing. Test results showed that LUI technique is capable of separating good chips from defective chips. Furthermore, LUI technique is able to reveal defect severity at each quadrant for each chip. Finally, chips were cross-sectioned and defects such as open and cracked solder bumps were observed. The cross-section results correlated well with LUI test results. This study demonstrates the feasibility and capability of this system on evaluating the solder bump quality on commercial products.

Void Inspection in Lead-Free Solder Bumps on Ball Grid Array (BGA) Packages Using Laser Ultrasound Technique

2011 ◽  
Author(s):  
Jie Gong ◽  
I. Charles Ume
Keyword(s):  
Ball Grid Array ◽  
Lead Free ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Lead Free Solder ◽  
X Ray ◽  
Bga Packages ◽  
Solder Bumps ◽  
Free Solder ◽  
Ultrasound Inspection

Solder joint voids are usually formed by the entrapped gas bubbles during the reflow process, and are common in all surface mount applications. It is a controversial issue on the reliability of the solder joint, however the consensus is that voiding is acceptable at low contents, while excessive voiding affects mechanical properties, and decreases strength, ductility and fatigue life of the interconnections. X-ray is the most widely used technique to evaluate the voids, including the size and occurrence frequency. In this paper, a laser ultrasound and interferometer inspection system is used to inspect the voids in lead-free solder bumps in ball grid array (BGA) packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; and laser interferometer is used to measure the transient out-of-plane displacement response of the package surface to the laser irradiation. The quality of solder bumps is evaluated by analyzing the transient responses. In this work, voids were intentionally created by adding the volatile flux during the assembly process. By controlling the volume of flux dip, three different levels of voiding were proposed: void-free, relatively low and relatively high. The presence of voids in the solder bumps was first verified using 2-D X-ray techniques. Meanwhile, the built-in image-processing software in X-ray tool measured the void fraction to quantify the level of voiding. Then the laser ultrasound inspection system was used to evaluate the voids in these samples. By comparing the vibration responses from voided samples and void-free samples, it was found that the laser ultrasound inspection system is capable to differentiate samples with relatively high voiding from void-free samples while the relatively low voiding was below the resolution of the inspection system. Lastly, a further comparison between the void-free and voided solder bumps was carried out by the destructive cross-section technique. The comparisons between these three solder bump evaluation methods will be presented in this paper.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter

2011 ◽  
Vol 2011 (1) ◽  
pp. 000985-000996 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Jörg Goßler ◽  
Jörg Franke
Keyword(s):  
Thermal Diffusion ◽  
Flip Chip ◽  
Solder Bump ◽  
Temperature Cycling ◽  
Sphere Diameter ◽  
Accelerated Life Tests ◽  
Flip Chips ◽  
Accelerated Life ◽  
Solder Bumps ◽  
Life Tests

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

Board-Level Solder Joint Reliability Study of Land Grid Array Packages for RF Application Using a Laser Ultrasound Inspection System

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Jin Yang ◽  
Lizheng Zhang ◽  
I. Charles Ume ◽  
Camil Ghiu ◽  
George White
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Thermal Loading ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Joint Quality ◽  
Ultrasound Inspection ◽  
Board Level

Microelectronics packaging technology has evolved from through-hole, and bulk configuration to surface-mount, and small-profile ones. Today’s electronics industry is also transiting from SnPb to Pb-free to meet environmental requirements. Land grid array (LGA) package has been becoming popular in portable electronics in terms of low profile on the printed wiring boards and direct Pb-free assembly process compatibility. With the package profile shrinking and operating power increasing, solder joint quality and reliability has become a major concern in microelectronics manufacturing. The solder joint failure at the package level or board level will cause electronic devices not to function during service. In this paper, board-level solder joint reliability of the LGA packages under thermal loading is studied through thermal cycling tests. A novel laser ultrasound-interferometric system developed by the authors is applied to inspect solder joint quality during the thermal cycling tests. While the laser ultrasound inspection technique has been successfully applied to flip chips and chip scale packages, this study is the first application of this technique to overmolded packages. In this study, it is found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints. The laser ultrasound inspection results match the visual observation and X-ray inspection results. This study demonstrates the feasibility of this system to solder joint quality inspection of overmolded packages. In particular, the devices constituting the objective of this study are radio frequency modules, which are encapsulated through overmolding and are mounted on a typical four-layer FR4 board through LGA terminations.

Application of a Novel Flip Chip Solder Joint Inspection System to Chips on an FR-4 Substrate

2000 ◽  
Author(s):  
Dathan S. Erdahl ◽  
Sheng Liu ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Bump ◽  
Solder Joints ◽  
Inspection System ◽  
Vibration Displacement ◽  
Manufacturing Defects ◽  
Flip Chips ◽  
Solder Joint Inspection

Abstract Because the trend in electronic interconnection technology is toward the development of solder bump technologies, that include flip chips, chip scale packages, multi-chip modules (MCMs), and ball grid array (BGA) packages, solder bump inspection methods must be developed to allow rapid, accurate, and high resolution on-line inspection of joint quality. Although traditional methods can detect some manufacturing defects, they do not actually test the mechanical quality of the connection. A novel solder-joint inspection system has been developed based on laser ultrasound and interferometric techniques. A pulsed laser generates ultrasound on the chip’s surface and the whole chip is excited into vibration modes. An interferometer is used to measure the vibration displacement of the chip’s surface. Solder joints with different qualities cause different vibration responses, acting as constraints on the system. The system was used to inspect the quality of solder joints on a group of flip chips mounted on FR-4 substrates, and the results show the ability of the system to detect defects such as missing solder balls, cracked chips, and gross misalignment.

scholarly journals Distance and Angle Correction System (DACS) for a kHz A-Scan Rate Pump-Probe Laser-Ultrasound Inspection

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7266
Author(s):  
Ryan A. Canfield ◽  
Jan Ahrens ◽  
Jill Bingham ◽  
Barry Fetzer ◽  
Thomas Müller-Wirts ◽  
...  
Keyword(s):  
Detection Efficiency ◽  
Numerical Aperture ◽  
Probe Laser ◽  
Depth Of Field ◽  
Polished Surface ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Angle Correction ◽  
Ultrasound Inspection ◽  
Correction System

Non-contact optical detection of ultrasound critically depends on the amount of light collected from the detection surface. Although it can be optimized in multiple ways for an ideal flat polished surface, industrial non-destructive testing and evaluation (NDT&E) usually requires optical detectors to be robust for unpolished material surfaces that are usually rough and curved. Confocal detectors provide the best light collection but must trade off sensitivity with depth of field. Specifically, detection efficiency increases with the numerical aperture (NA) of the detector, but the depth of field drops. Therefore, fast realignment of the detector focal point is critical for in-field applications. Here, we propose an optical distance and angle correction system (DACS) and demonstrate it in a kHz-rate laser-ultrasound inspection system. It incorporates a Sagnac interferometer on receive for the fast scanning of aircraft composites, which minimizes the required initial alignment. We show that DACS performs stably for different composite surfaces while providing ±2° angular and ±2 mm axial automatic correction with a maximum 100 ms realignment time.

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