The Effect of Intermetallic Growth on Bump Pull Test Responses of SAC105 Solder Bumps

2009 ◽  
Vol 131 (4) ◽  
Author(s):  
Jose Omar S. Amistoso ◽  
Alberto V. Amorsolo
Keyword(s):  
Failure Modes ◽  
Solder Bump ◽  
Diffusion Processes ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Intermetallic Growth ◽  
Solder Bumps ◽  
Sac105 Solder ◽  
Solder Bulk ◽  
Pull Tests

Cold bump pull tests performed on wafer level chip scale packages using SAC105 solder bumps show an increase in the occurrence of brittle failure modes with aging temperature and time. Fast intermetallic growth at 0–1000 h can be attributed to (Cu,Ni)6Sn5, while the decrease in intermetallic growth rate at t>1000 h can be attributed to diffusion processes leading to (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 formation and growth. Ni diffuses toward the solder bulk and saturates at 175–200°C, while Cu diffuses from the under bump metallization (UBM) toward the solder bump at 125–150°C. Interactions between Cu and Ni atoms lead to saturation of their atomic % gradients due to intermetallic formation. Sn diffusion from the solder toward the UBM occurs at 125–150°C. The activation energy for total intermetallic growth was calculated at 0.2 eV.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Jia Xi ◽  
Xinduo Zhai ◽  
Jun Wang ◽  
Donglun Yang ◽  
Mao Ru ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
High Stress ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Element Analysis ◽  
Drop Tests ◽  
Feni Alloy

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Interfacial Reaction and Bump Shear Property of Electroplated Sn-37Pb Solder Bump with Ni under Bump Metallization during Multiple Reflows

2006 ◽  
Vol 15-17 ◽  
pp. 181-186
Author(s):  
Ja Myeong Koo ◽  
Seung Boo Jung
Keyword(s):  
Intermetallic Compound ◽  
Brittle Fracture ◽  
Interfacial Reaction ◽  
Solder Bump ◽  
Ductile Failure ◽  
Under Bump Metallization ◽  
Shear Properties ◽  
Failure Characteristics ◽  
Shear Property ◽  
Solder Bumps

The interfacial reactions and bump shear properties of the electroplated Sn-37Pb (in wt.%) solder bumps with the Ni under bump metallization (UBM) were investigated as a function of the number of reflows. A continuous facetted Ni3Sn4 intermetallic compound (IMC) layer was formed at the interface between the solder bump and the Ni UBM during reflow. The thickness of the Ni3Sn4 IMC layer was 0.41 μm after 1 reflow, and then the thickness of the IMC layer increased with increasing the number of reflows. The shear properties of the bumps indicated the maximum values after 1 reflow, and then decreased with increasing the number of reflows. The fracture surfaces of the bumps showed ductile failure characteristics after 1 reflow, and then the fraction of the brittle fracture, induced by the IMC formed at the interface, increased with increasing the number of reflows.

Reliability analysis of Au–Sn flip-chip solder bump fabricated by co-electroplating

2007 ◽  
Vol 22 (5) ◽  
pp. 1219-1229 ◽  
Author(s):  
Jeong-Won Yoon ◽  
Hyun-Suk Chun ◽  
Seung-Boo Jung
Keyword(s):  
Brittle Failure ◽  
Flip Chip ◽  
Solder Bump ◽  
Solder Matrix ◽  
Average Diameter ◽  
Under Bump Metallization ◽  
Mechanical Reliability ◽  
Shear Tests ◽  
Solder Bumps ◽  
Δ Phase

In this study, we fabricated eutectic Au–Sn (Au–20 wt% Sn) flip-chip solder bumps from a single electroplating bath. After reflowing, the average diameter of the solder bump was approximately 80 μm. The (Ni,Au)3Sn2 phase was initially formed when the liquid Au–Sn solder reacted with the Ni UBM (under bump metallization). After aging at 150 °C, the (Ni,Au)3Sn2 intermetallic compound (IMC), which formed at the interface during reflow, was fully transformed into the (Au,Ni)Sn IMC due to the restricted supply of Ni atoms from the UBM to the interface. On the other hand, after aging at 250 °C for 1000 h, two IMC layers, (Au,Ni)Sn and (Ni,Au)3Sn2, were formed at the interface. The lower (Ni,Au)3Sn2 phase was formed when the (Au,Ni)Sn phase reacted with the Ni UBM. The interfacial (Au,Ni)Sn IMC grew with the preferential consumption of the available δ-phase in the solder matrix. Eventually, the ζ-phase covered most of the interfacial layer. In the bump shear tests, the Au–Sn/Ni joint aged at 150 °C fractured through the bulk of the solder, confirming the mechanical reliability of the interface. In contrast, the Au–Sn/Ni joint aged at 250 °C fractured along the interface, thereby demonstrating brittle failure, possibly a result of the brittle IMC layer at the interface.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Diagram of Electromigration Pattern in Eutectic Pb-Sn and Pb-Free Solders

2005 ◽  
Vol 297-300 ◽  
pp. 837-843
Author(s):  
Takashi Hasegawa ◽  
Masumi Saka
Keyword(s):  
Current Density ◽  
Solder Bump ◽  
High Density ◽  
Solder Bumps ◽  
Multi Phase ◽  
High Density Packaging

Solder is the most frequently used alloy, which serves as the bonding metal for electronics components. Recently, the interconnected bump is distinctly downsizing its bulk along with the integration of high-density packaging. The evaluation of electromigration damage for solder bumps is indispensable. Hence, it is fairly urgent to understand the mechanism of the electromigration damage to be capable of securing reliability of the solder bump and ultimately predicting its failure lifetime. Electromigration pattern in multi-phase material is determined by the combination of current density, temperature and current-applying time. In this paper, diagram of electromigration pattern (DEP) in solders is presented, where both of eutectic Pb-Sn and Pb-free solders are treated. DEP gives the basis for discussing and predicting the electromigration damage in solders.

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

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