Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Jia Xi ◽  
Xinduo Zhai ◽  
Jun Wang ◽  
Donglun Yang ◽  
Mao Ru ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
High Stress ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Element Analysis ◽  
Drop Tests ◽  
Feni Alloy

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Reliability of Interconnections Made of Sintered Silver Nano Particles

2015 ◽  
Author(s):  
Przemyslaw K. Matkowski ◽  
Tomasz Falat ◽  
Andrzej Moscicki
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Nano Particles ◽  
Circuit Board ◽  
X Ray ◽  
Detection Failure ◽  
X Ray Computed ◽  
Sintered Silver

This study investigates the effect of silver paste composition on reliability of sintered silver interconnections. The interconnections are formed between SMD 1206 chip jumpers and electroless nickel immersion gold (ENIG) coating of FR4 printed circuit board (PCB) solder pads. They are made of pastes that vary in their composition (various proportions of micro and nano particles). The sintering process was conducted in convective oven. After the process the interconnections were subjected to X-Ray inspection in order to characterize the structure of interconnections (presence of voids, total surface of interconnection etc.). During accelerated reliability tests the PCBs were subjected to combined temperature cycling and vibration loading. During the tests daisy chains of interconnections were connected to dedicated programmable multichannel event detector developed in LIPEC lab. The event detector is able to detect and store information about object condition based on the real-time resistance measurements and applied novel algorithm of event detection. Failure modes were confirmed by using X-Ray computed tomography. The paper presents results of comparative Weibull analysis.

scholarly journals Sporadic Early Life Solder Ball Detachment Effects on Subsequent Microstructure Evolution and Fatigue of Solder Joints in Wafer-Level Chip-Scale Packages

2020 ◽  
Vol 17 (1) ◽  
pp. 13-22
Author(s):  
Simon Schambeck ◽  
Matthias Hutter ◽  
Johannes Jaeschke ◽  
Andrea Deutinger ◽  
Martin Schneider-Ramelow
Keyword(s):  
Thermal Loading ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Aging Effects ◽  
Chip Scale Package ◽  
Solder Balls

Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packaging technology. One aspect is to increase the understanding of the damage under environmental loading. Therefore, the solder joints of a wafer-level chip-scale package assembled on a printed circuit board (PCB) have been analyzed after a temperature cycling test. In the case of the investigated package, a limited number of joints did not form a proper mechanical connection with the PCB copper pad. Although not intended in the first place, these circumstances cause a detachment of those joints within the first few thermal cycles. However, this constellation offers a unique opportunity to compare the solder joint microstructure after thermomechanical loading (connected joints) with pure thermal loading (detached joints) located directly next to each other. It is shown that microstructure aging effects can be directly linked to regions in the joint with increased loading. This is particularly the case for detached joints, which could almost retain their initial microstructure up to the effect of the high-temperature part of the thermal profile. By means of finite element simulation, it is further possible to quantify the increased loading on adjacent joints if isolated solder balls detach from the board. In one case presented, the lifetime of the corner joint was calculated to reduce up to 85% only.

Effects of Void, Crack, and PCB Thickness on the Solder Joint Reliability of Wafer-Level Chip-Scale Package (WLCSP) Assemblies

2002 ◽  
Author(s):  
John Lau ◽  
Yida Zou ◽  
Sergio Camerlo
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Temperature Cycling ◽  
Circuit Board ◽  
J Integral ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Printed Circuit ◽  
Joint Reliability ◽  
Chip Scale Package

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Lei Shi ◽  
Lin Chen ◽  
David Wei Zhang ◽  
Evan Liu ◽  
Qiang Liu ◽  
...  
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Equivalent Stress ◽  
Circuit Board ◽  
Electrical Performance ◽  
Design Parameters ◽  
Wafer Level ◽  
Element Analysis

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

scholarly journals Design and Reliability Assessment of Novel 3D-IC Packaging

2016 ◽  
Vol 33 (2) ◽  
pp. 193-203 ◽  
Author(s):  
Y.-F. Su ◽  
K.-N. Chiang ◽  
Steven Y. Liang
Keyword(s):  
Electronic Packaging ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Material Design ◽  
Circuit Board ◽  
Wafer Level ◽  
Element Analysis ◽  
Moore’S Law ◽  
Moore's Law

AbstractPresently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

Dynamic – Thermal Analyses of a Structurally Reconfigured Electronics Package Onboard Mini Satellite

2014 ◽  
Vol 592-594 ◽  
pp. 2117-2121 ◽  
Author(s):  
P. Veeramuthuvel ◽  
S. Jayaraman ◽  
Shankar Krishnapillai ◽  
M. Annadurai ◽  
A.K. Sharma
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Thermal Environment ◽  
Thermal Analyses ◽  
Simulation Models ◽  
Element Model ◽  
Circuit Board ◽  
Element Analysis ◽  
Transfer Path ◽  
Vibration Responses

The electronics package in a spacecraft is subjected to a variety of dynamic loads during launch phase and suitable thermal environment for the mission life. The dynamic and thermal analyses performed for a structurally reconfigured electronics package. Two different simulation models are developed to carry out the analyses. This paper discusses in two parts, in part-1, the vibration responses are determined at various critical locations, including on the Printed Circuit Board (PCB) for the vibration loads specified by launch vehicle using Finite Element Analysis (FEA). The mechanical properties of PCB are determined from the test specimens, which are then incorporated in the finite element model. In part-2, the steady-state temperature distributions on the components and on the PCB are determined, to check the effectiveness of heat transfer path from the components to the base of the package and to verify the predicted values are within the acceptable temperature limits specified. The predicted temperature values are then compared with on-orbit observations.

In-Plane Electromagnetic Generator Fabricated on Printed Circuit Board Technology

2013 ◽  
Vol 479-480 ◽  
pp. 524-529
Author(s):  
C.T. Pan ◽  
F.T. Hsu ◽  
C.C. Nien ◽  
Z.H. Liu ◽  
Y.J. Chen ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Energy Harvester ◽  
Cost Effective ◽  
Circuit Board ◽  
Outer Diameter ◽  
Magnetic Element ◽  
Induced Voltage ◽  
Element Analysis ◽  
Printed Circuit ◽  
Electromagnetic Generator

Small and efficient energy harvesters, as a renewable power supply, draw lots of attention in the last few years. This paper presents a planar rotary electromagnetic generator with copper coils fabricated by using printed circuit board (PCB) as inductance and Nd-Fe-B magnets as magnetic element. Coils are fabricated on PCB, which is presumably cost-effective and promising methods. 28-pole Nd-Fe-B magnets with outer diameter of 50 mm and thickness of 2 mm was sintered and magnetized, which can provide magnetic field of 1.44 Tesla. This harvester consists of planar multilayer with multi-pole coils and multi-pole permanent magnet, and the volume of this harvester is about 50x50x2.5 mm3. Finite element analysis is used to design energy harvesting system, and simulation model of the energy harvester is established. In order to verify the simulation, experiment data are compared with simulation result. The PCB energy harvester prototype can generate induced voltage 0.61 V and 13.29mW output power at rotary speed of 4,000 rpm.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

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