Experimental Analysis of Thermal Cycling Fatigue of Four-Layered FR4 Printed Wiring Boards

1994 ◽  
Vol 116 (2) ◽  
pp. 76-82 ◽  
Author(s):  
Tsung-Yu Pan ◽  
Ronald R. Cooper ◽  
Howard D. Blair ◽  
Thomas J. Whalen ◽  
John M. Nicholson
Keyword(s):  
Thermal Cycling ◽  
Electrical Resistance ◽  
Crack Model ◽  
Electronic Packages ◽  
Printed Wiring Boards ◽  
Element Analysis ◽  
Mechanics Model ◽  
Plated Through Hole ◽  
Thermal Cycling Fatigue ◽  
Factor Interactions

Long-term reliability of electronic packaging has become a greater challenge as a result of ever increasing power requirements and the decreasing size of electronic packages. In this study, the effects of three variables on plated-through hole (PTH) design have been investigated on the thermal cycling fatigue lives in four-layered printed wiring boards (PWB’s). These three variables were evaluated at two levels each: (a) hole size (0.030 and 0.040 in.), (b) internal pad (presence or absence), and (c) epoxy-plugged holes (plugged or unplugged). The electrical resistance was measured on 40 test boards with 23 design of 8 daisy-chain PTH nets each. Full factorial analysis and analysis of variance indicate that all three factors had significant influence on PTH fatigue life, but no two-factor or three-factor interactions were found. Metallurgical analysis reveals that the failure mechanism is barrel cracking near the internal pad. This mechanism has been illustrated by a finite element analysis in this study and correlated by a SEM stereoimaging analysis in the literature. The increase of electrical resistance with thermal cycles correlates well with an analytical barrel crack model. The crack length in each net at specific cycles is calculated, but fails to match predictions from a fracture mechanics model.

An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls

2007 ◽  
Vol 129 (4) ◽  
pp. 427-433 ◽  
Author(s):  
Krishna Tunga ◽  
Suresh K. Sitaraman
Keyword(s):  
Thermal Cycling ◽  
Experimental Technique ◽  
Electronic Packages ◽  
Solder Balls ◽  
Bga Package ◽  
Accelerated Thermal Cycling ◽  
Thermal Cycling Fatigue ◽  
Number Of Cycles ◽  
Thermomechanical Reliability ◽  
Ball Grid Array Packages

Although accelerated thermal cycling has been widely used in electronics industry to qualify electronic packages, efforts to reduce the time and cost associated with such qualification techniques are continuously being sought. This paper outlines a laser-moiré based experimental technique to quickly assess the thermal cycling reliability of microelectronic packages. Unlike accelerated thermal cycling that takes several months to complete, the proposed technique takes one to two weeks to complete and does not suffer from various modeling assumptions used in finite-element simulations. The developed technique has been used to determine the thermomechanical reliability of organic and ceramic ball grid array packages, and it is shown that the number of cycles determined by the proposed technique is comparable to the number of cycles determined through accelerated thermal cycling.

Finite element analysis on the thermal fatigue life of full vs peripheral array packages

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Mohammad A. Gharaibeh
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Fatigue Life ◽  
Thermal Cycling ◽  
Thermal Fatigue ◽  
Three Dimensional ◽  
Element Analysis ◽  
Content Type ◽  
Thermal Fatigue Life ◽  
Thermal Cycling Fatigue

PurposeThis paper aims to examine the thermal cycling fatigue life performance of two-common solder array configurations, full and peripheral, using three-dimensional nonlinear finite element analysis.Design/methodology/approachThe finite element simulations were used to identify the location of the critical solder interconnect, and using Darveaux's model, solder thermal fatigue life was computed.FindingsThe results showed that the solder array type does not significantly influence thermal fatigue life of the interconnect. However, smaller size packages result in improved life by almost 45% compared to larger package designs. Additionally, this paper provided an engineered study on the effect of the number of rows available in a perimeter array component on solder thermal fatigue performance.Originality/valueGeneral design recommendations for reliable electronic assemblies under thermal cycling loaded were offered in this research.

An Optical Method for Measuring the Two-Dimensional Surface Curvatures of Electronic Packages During Thermal Cycling

2000 ◽  
Vol 123 (3) ◽  
pp. 196-199 ◽  
Author(s):  
Yong Du ◽  
Jie-Hua Zhao ◽  
Paul Ho
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Thermal Cycling ◽  
Optical Method ◽  
Flip Chip ◽  
Laser Beams ◽  
Electronic Packages ◽  
Two Dimensional ◽  
Element Analysis ◽  
Dimensional Surface

An optical method was developed to measure the two-dimensional (2D) surface curvatures of electronic packages by employing four laser beams. Each laser beam measures the slopes of the surface at the incident point along two perpendicular directions. By combining four pairs of slopes, the 2D surface curvatures of the package can be calculated. The surface warpage of an underfilled flip-chip package during thermal cycling was measured by this method and the result was verified by finite element analysis (FEA). Both experimental and FEA results show that the surface warpage is almost a linear function of temperature between 25°C and 150°C for the measured package.

Thermomechanical Stress and Warpage Augmentation Using Auxetic Features in Electronic Design

2019 ◽  
Author(s):  
Mahsa Montazeri ◽  
John Harris ◽  
David R. Huitink ◽  
Adithya Venkatanarayanan ◽  
Simon S. Ang
Keyword(s):  
Thermal Cycling ◽  
Stress Reduction ◽  
Coefficient Of Thermal Expansion ◽  
Ground Plane ◽  
Tensile Load ◽  
Maximum Temperature ◽  
Electronic Packages ◽  
Element Analysis ◽  
Interfacial Stresses ◽  
Auxetic Structures

Abstract One of the leading contributors to assembly and reliability issues in electronic packaging arises from warpage and interfacial stresses stemming from coefficient of thermal expansion (CTE) mismatch of the interfacing components. Trends toward miniaturizing and increasing density of the electronic packages exacerbate the assembly problems, leading to issues such as die cracking and board level assembly yield loss. One potential solution may be found in the inclusion of auxetic structures, which demonstrate negative Poisson’s ratio through re-entrant geometries, which has been investigated for use in augmented structural mechanics for impact energy absorption. Because of the unique structural design, auxetics become thicker perpendicularly under an applied tensile load, unlike typical material loading responses. This interesting behavior has opportunity for integration into electronic packages for stress mitigation under thermal cycling since the structures can disrupt the typical expansion behavior. Here, auxetic trace geometries and structures were evaluated in various packaging implementations (die and substrate level) for warpage and stress reduction under thermal cycling conditions. By replacing standard Manhattan-style layouts and power and ground plane features with re-entrant trace geometries, reductions in thermomechanically induced interfacial stresses were observed, in addition to considering heat spreading properties within a package. Herein, deformation of silicon chip with addition of raised re-entrant Evans auxetics and raised ellipse shape auxetic traces as well as deformation of direct bonded copper (DBC) substrate with and without re-entrant auxetic patterned pads are estimated and compared using Finite Element Analysis (FEA) in ANSYS software. To demonstrate the benefits of passive auxetic traces, a planar transformer with re-entrant Evans auxetic patterns on PCB layers has been examined under full-load operating condition and compared with a traditionally patterned transformers. A better thermal distribution and lower maximum temperature in the device are achieved by including auxetic patterned features. FEA simulation results also show stress reduction in windings and lower deformation in PCB layers. Inclusion of auxetic structures in passive metal deposition layers which are not part of the circuit is shown to reduce maximum stress and warp deflection, as well as improve thermal gradient distribution and reduce overall temperature for 2D planar and 3D stacked packages. Consequently, use of auxetic features may extend package reliability significantly.

Evaluation of Smear and Its Effect on the Mechanical Integrity of Plated Through Hole-Inner Plane Interface in Thick Printed Wiring Boards

2000 ◽  
Vol 123 (1) ◽  
pp. 6-15 ◽  
Author(s):  
R. Venkatraman ◽  
K. Ramakrishna ◽  
K. Knadle ◽  
W. T. Chen ◽  
G. C. Haddon
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Failure Mechanism ◽  
Stress Testing ◽  
Large Strain ◽  
Peel Test ◽  
Stress Tests ◽  
Printed Wiring Boards ◽  
Element Analysis ◽  
Plated Through Hole

In multi-layer printed wiring boards (PWBs), electrical connections between different layers are accomplished with plated through holes (PTHs). The reliability of the PTH barrel and the PTH-inner plane (IP) connection depends not only on the design but also on the conditions of manufacturing and assembly processes of the board. The concerns associated with manufacturing arise from drilling which heats up and smears the surrounding epoxy onto the copper inner plane surfaces and also from subsequent chemical hole-clean operations which desmear the drilled holes. Good adhesion of the PTH copper to the desmeared PTH wall and to the copper inner planes is important for the reliability of the PTHs during assembly and field service. PWB coupons consisting of resin-glass bundle areas as well as resin filled clearance areas surrounding the PTH have been considered for a series of experiments and tests. On these coupons, accelerated stress tests and failure analysis of the PTHs at the end of these tests have been conducted. An elasto-plastic finite element analysis of the PTH strains for a temperature excursion of 102°C has been carried out for signal PTHs without and with IP connections. A peel test, using a micro-mechanical tester, has also been carried out to assess the adhesion of PTH copper to different regions along the drilled hole. All of the testing techniques have been supplemented by suitable analytical techniques for studying the distribution of smear on the copper inner planes. A birefringence technique to estimate the temperature of the hole wall during drilling has been described. All of the fails observed during stress testing are in the form of cracks in the PTH barrel, the plane of the crack being perpendicular to the barrel axis. The cracks are localized near the glass bundle-resin rich interface. It has also been observed in the failure analysis that the PTH/IP connections are not susceptible to failure during the accelerated stress testing conditions considered. These observations are also supported by the results of stress analysis. The results of stress analysis show that the interior clearance holes show higher strains than those closer to board surfaces, suggesting that the PTH barrel failure is likely to occur at the clearance hole and that the likelihood of failure at the interior clearance holes is higher than those closer to the PWB surfaces. The results of the peel test reveal that in the glass bundle-resin regions, the adhesion along the PTH wall is determined by the mechanical interlocking between the plated copper and the glass bundles and is relatively insensitive to desmear operations. However, adhesion in the resin-rich areas is a strong function of the desmear operation, which enhances the adhesion of the PTH to the resin. Finally, it is shown that the birefringence technique may be used effectively to estimate the drilling temperature and, hence, the degree of smearing and PTH quality. It is concluded that while smear may play an important role in the failure of PTHs in PWBs, for thick packaging boards with high aspect ratio PTHs, the predominant failure mechanism is less likely to be smear related. Such a failure mechanism would be preceded by failure in the PTH barrels as a result of the large strain concentrations imposed at specific locations within the cross-section.

scholarly journals Bonding and Thermal Cycling Performances of Two (Poly)Aryl–Ether–Ketone (PAEKs) Materials to an Acrylic Denture Base Resin

Polymers ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 543 ◽  
Author(s):  
Tzu-Yu Peng ◽  
Saiji Shimoe ◽  
Lih-Jyh Fuh ◽  
Chung-Kwei Lin ◽  
Dan-Jae Lin ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Thermal Cycling ◽  
Fatigue Testing ◽  
Lower Surface ◽  
Aryl Ether ◽  
Bonding Performance ◽  
Significant Difference ◽  
Aryl Ether Ketone ◽  
Ether Ketone ◽  
Thermal Cycling Fatigue

Poly(aryl–ether–ketone) materials (PAEKs) are gaining interest in everyday dental practices because of their natural properties. This study aims to analyze the bonding performance of PAEKs to a denture acrylic. Testing materials were pretreated by grinding, sandblasting, and priming prior to polymerization with the denture acrylic. The surface morphologies were observed using a scanning electron microscope and the surface roughness was measured using atomic force microscopy. The shear bond strength (SBS) values were determined after 0 and 2500 thermal cycles. The obtained data were analyzed using a paired samples t-test and Tukey’s honestly significant difference (HSD) test (α = 0.05). The surface characteristics of testing materials after different surface pretreatments showed obvious differences. PAEKs showed lower surface roughness values (0.02–0.03 MPa) than Co-Cr (0.16 MPa) and zirconia (0.22 MPa) after priming and sandblasting treatments (p < 0.05). The SBS values of PAEKs (7.60–8.38 MPa) met the clinical requirements suggested by ISO 10477 (5 MPa). Moreover, PAEKs showed significantly lower SBS reductions (p < 0.05) after thermal cycling fatigue testing compared to Co-Cr and zirconia. Bonding performance is essential for denture materials, and our results demonstrated that PAEKs possess good resistance to thermal cycling fatigue, which is an advantage in clinical applications. The results imply that PAEKs are potential alternative materials for the removable of prosthetic frameworks.

Lifetime Prediction of Components Including Initiation Phase

2006 ◽  
Author(s):  
Michael Besel ◽  
Angelika Brueckner-Foit
Keyword(s):  
Input Data ◽  
Local Stress ◽  
Fatigue Loading ◽  
Computer Code ◽  
Lifetime Distribution ◽  
Element Analysis ◽  
Initiation Phase ◽  
Mechanics Model ◽  
Critical Regions ◽  
Local Stress Field

The lifetime distribution of a component subjected to fatigue loading is calculated using a micro-mechanics model for crack initiation and a fracture mechanics model for crack growth. These models are implemented in a computer code which uses the local stress field obtained in a Finite Element analysis as input data. Elemental failure probabilities are defined which allow to identify critical regions and are independent of mesh refinement. An example is given to illustrate the capabilities of the code. Special emphasis is put on the effect of the initiation phase on the lifetime distribution.

A Highly Accelerated Thermal Cycling (HATC) Test for Solder Reliability Assessment in BGA Packages

2007 ◽  
Author(s):  
X. Long ◽  
I. Dutta ◽  
R. Guduru ◽  
R. Prasanna ◽  
M. Pacheco
Keyword(s):  
Thermal Cycling ◽  
Solder Joints ◽  
Low Cycle Fatigue ◽  
Inelastic Strain ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Mechanical Cycling ◽  
Experimental Apparatus ◽  
Dependent Strain ◽  
Accelerated Thermal Cycling

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

An Interfacial Delamination Analysis for Multichip Module Thin Film Interconnects

1996 ◽  
Vol 118 (4) ◽  
pp. 206-213 ◽  
Author(s):  
K. X. Hu ◽  
C. P. Yeh ◽  
X. S. Wu ◽  
K. Wyatt
Keyword(s):  
Thin Film ◽  
Phase Angle ◽  
Structural Reliability ◽  
Thermal Loading ◽  
Multichip Module ◽  
Crack Model ◽  
Element Analysis ◽  
Delamination Growth ◽  
Interfacial Delamination ◽  
Functional Behavior

Analysis of interfacial delamination for multichip module thin-film interconnects (MCM/TFI) is the primary objective of this paper. An interface crack model is integrated with finite-element analysis to allow for accurate numerical evaluation of the magnitude and phase angle of the complex stress intensity factor. Under the assumption of quasi-static delamination growth, the fate of an interfacial delamination after inception of propagation is determined. It is established that whether an interfacial delamination will continue to grow or become arrested depends on the functional behavior of the energy release rate and loading phase angle over the history of delamination growth. This functional behavior is numerically obtained for a typical MCM/TFI structure with delamination along die and via base, subjected to thermal loading condition. The effect of delamination interactions on the structural reliability is also investigated. It is observed that the delamination along via wall and polymer thin film can provide a benevolent mechanism to relieve thermal constraints, leading to via stress relaxation.

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