Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials

2006 ◽  
Vol 128 (4) ◽  
pp. 405-411 ◽  
Author(s):  
Saketh Mahalingam ◽  
Kunal Goray ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Fatigue Loading ◽  
Experimental Characterization ◽  
Material Interfaces ◽  
Interfacial Delamination ◽  
Mechanical Fatigue ◽  
Fine Pitch ◽  
Processing Steps ◽  
Delamination Propagation

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.

Electrical Characterization of NCP- and NCF-Bonded Fine-Pitch Flip-Chip-on-Flexible Packages

2007 ◽  
Vol 30 (1) ◽  
pp. 142-147 ◽  
Author(s):  
Y. C. Chan ◽  
S. C. Tan ◽  
Nelson S. M. Lui ◽  
C. W. Tan
Keyword(s):  
Flip Chip ◽  
Electrical Characterization ◽  
Fine Pitch

Electrical Characterization of NCP- and NCF-Bonded Fine-Pitch Flip-Chip-on-Flexible Packages

2006 ◽  
Vol 29 (4) ◽  
pp. 735-740 ◽  
Author(s):  
Y. C. Chan ◽  
S. C. Tan ◽  
Nelson S. M. Lui ◽  
C. W. Tan
Keyword(s):  
Flip Chip ◽  
Electrical Characterization ◽  
Fine Pitch

The Characterization of Underfill-Passivation Interface Under Monotonic and Fatigue Loading and Its Application to Flip Chip Reliability Prediction

2005 ◽  
Author(s):  
Saketh Mahalingam ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Reasonable Agreement ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Reliability Prediction ◽  
Paris Law ◽  
Joint Reliability ◽  
Electrical Interconnection ◽  
Flip Chip Packaging ◽  
Underfill Material

Flip chip packaging technology is an attractive technique to achieve mechanical and electrical interconnection between the silicon chip and the substrate. Solder joint reliability in flip chip on organic board (FCOB) is enhanced by underfill application. The failure of solder joints in a flip chip package is usually associated with underfill delamination, esp. from the chip passivation. In this work, the fracture toughness of this interface is characterized for a novel no-flow underfill material using an innovative residual stress induced decohesion (RSID) test. Numerical modeling of the chip passivation-underfill interface indicates that the delamination will not progress under monotonic loading. However, the progress of delamination occurs under repeated thermal cycling. An empirical Paris law for underfill delamination has been developed and has been applied to predict delamination in actual flip chip packages. A reasonable agreement between the two is shown.

Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Saketh Mahalingam ◽  
Ananth Prabhakumar ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Experimental Data ◽  
Thermal Shock ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Thermomechanical Fatigue ◽  
Interfacial Delamination ◽  
Shock Testing ◽  
Solder Bumps ◽  
Theoretical Predictions ◽  
Flip Chip Assembly

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.

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