Assembly Yields Characterization of High IO Density, Fine Pitch Flip Chip in Package Using No-Flow Underfill

Author(s):  
Sangil Lee ◽  
Daniel F. Baldwin ◽  
Raj Master ◽  
Srinivasan Parthasarathy
Keyword(s):  
2007 ◽  
Vol 30 (1) ◽  
pp. 142-147 ◽  
Author(s):  
Y. C. Chan ◽  
S. C. Tan ◽  
Nelson S. M. Lui ◽  
C. W. Tan

2006 ◽  
Vol 29 (4) ◽  
pp. 735-740 ◽  
Author(s):  
Y. C. Chan ◽  
S. C. Tan ◽  
Nelson S. M. Lui ◽  
C. W. Tan

2006 ◽  
Vol 128 (4) ◽  
pp. 405-411 ◽  
Author(s):  
Saketh Mahalingam ◽  
Kunal Goray ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.


2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  

2012 ◽  
Vol 159 (9) ◽  
pp. D532-D537 ◽  
Author(s):  
Rajarshi Saha ◽  
Hyo-Chol Koo ◽  
Ping Nicole An ◽  
Paul A. Kohl

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.


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