Prediction of Thermal Performance of Wire-Bonded Plastic Ball Grid Array Package for Underhood Automotive Applications

2003 ◽  
Vol 125 (3) ◽  
pp. 447-455 ◽  
Author(s):  
K. Ramakrishna ◽  
J. R. Trent

Thermal performance of a three chip, overmolded wire-bonded plastic ball grid array (WB-PBGA) package with four layer substrate attached to a 1.52-mm-thick, four-layer (2s2p), FR4 printed wiring board (PWB) has been evaluated under horizontal natural convection conditions for underhood automotive applications as a function of ambient temperature, package design parameters, and thermophysical properties of the package and PWB materials. A two-tier modeling approach, which accurately accounts for multidimensional heat transfer effects caused by substrate features such as vias and C5 solder joints, has been developed and implemented. In this methodology, the effect of small features is first characterized using a detailed micromodel from which an effective thermal conductivity is computed. The effective thermal conductivity is implemented in the global model thereby excluding the small features in the global model. The actual stackups of the package and PWB have been used in the computations to accurately determine the in-plane heat spreading. Using this methodology for automotive underhood applications, a parametric study of thermal performance of the WB-PBGA package has been carried out. This study shows that: 1. The maximum junction temperature rise above ambient, ΔT, decreases with increase in ambient temperature by 30% as the ambient temperature increases from 23 to 125°C. 2. ΔT decreases by 20% as the emissivity of the molding compound and the PWB surfaces increases from 0 (no radiative loss) to 0.8 under natural convection conditions. 3. The decrease in ΔT is small (∼7%) as the thermal conductivity of the die attach material varies over a wide range. 4. ΔT decreases by 30% as the thermal conductivity of the molding compound is varied over a wide range. 5. ΔT decreases by 45% as the thermal conductivity of the substrate increases (i.e., as the number of vias in the substrate increase) from no vias case to densely populated vias.

Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee

Flip-chip plastic ball grid array (FC-PBGA) packages are fast becoming the industry norm, in particular in the performance and cost driven consumer electronics sector. Since high thermal conductivity (k∼15–20 W/(m K)) ceramic substrate is replaced by a low conductivity (k∼0.2–0.5 W/(m K)) organic substrate in the FC-PBGA packages, enhancement of thermal performance of these packages to meet ever increasing demands is crucial for their wide spread use. In this study, enhancements to thermal performance of FC-PBGA packages due to material and design changes and external means such as heat spreaders and overmolding of the packages have been evaluated by solving a conjugate heat transfer models using the methods of computational fluid dynamic. The thermal enhancements evaluated in this study include the effect of thermal conductivity of the chip to package interconnect due to change in underfill material and the C4 bump pitch, effect of package to printed wiring board (PWB) interconnection through the use of thermal balls, effect of a heat spreader on the backside of the die, and overmolding the die without and with a heat spreader. Thermal performance of the FC-PBGA packages have been studied using junction to ambient thermal resistance, Θja, junction-to-board thermal resistance Ψjb, and junction to case thermal resistance ΨjT under natural and forced convection for freestream velocities up to 2 m/s and the for following ranges of parameters: Substrate size: 25 to 35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), C4 pitch: 250 mm, 150 mm and below, underfill material thermal conductivity: 0.6 to 3.0 W/(m K), no thermal balls between the package and the PWB to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of the bare and overmolded die. Based on previous experience, predictions in this study are expected to be within ±10% of measured data. The following conclusions are drawn from this study: 1. It is concluded that the thermal conductivity of the underfill materials in the range 0.6 to 10 W/(m K) is negligible. 2. It is also concluded that the bump pitch can decrease thermal resistances by 12 to 15 %. The change may be smaller with large die area. 3. Thermal balls (C5) connected to the PTHs in the PWB can decrease thermal resistance by about 10% to 15% as the number of thermal balls & PTHs increase zero to 9×9 on 1.27 mm pitch. The effect die size on this thermal enhancement is more noticeable on Ψjb. 4. Heat spreader on the back of the die decreases Θja by a small amount (6–7%) in natural convection and a large amount, about 25% in forced convection. 5. Overmolded die with heat spreader on the top of the overmold provides better thermal enhancement than heat spreader alone up to about 1 m/s. Beyond 1 m/s, heat spreader (without overmold) performs slightly better.


2001 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Lee

Abstract Package level thermal performance of flip-chip plastic ball grid array (FC-PBGA) packages has been predicted using experimentally validated mechanistic methodologies. The resulting conjugate heat transfer models have been solved using methods of computational fluid dynamics under natural and forced convection for freestream velocities up to 2 m/s. Overall junction to ambient, Θja, junction-to-board, Ψjb, and junction to case Ψjτ thermal resistances (here after referred to as thermal parameters) have been derived from the results of these computations. Using these models and methodologies, which are previously validated against experimental data, a parametric study of effect of die size on the package thermal parameters has been carried out for die sizes in the range 2 to 20 mm (area of 4–400 mm2) under natural and forced convection with freestream velocities in the range of 0.5 to 2 m/s. The predictions in this study are expected to be ±10% of the measured data. Based on this work the following conclusions have been drawn: 1. The junction to ambient, Θja, and junction to board, Ψjb, thermal resistances decrease with increase in freestream velocity, U, and junction to case thermal resistance, Ψjτ, increases with U. Ψjb shows a weaker dependence on U than Θja does. 2. For a fixed substrate size, package thermal resistances, Θja and Ψjb, decrease as the die size increases from 2 mm (4 mm2) to 20 mm (400 mm2). However, these resistances reach asymptotic values for die sizes above 50 mm2. The change in these resistances is in the range 20% to 35% and the effect of freestream velocity on the percentage changes is small. 3. An extensive database of experimentally validated FC-PBGA package thermal parameters have been generated for a wide range of die sizes.


Author(s):  
Luis A. Curiel ◽  
Andrew J. Komrowski ◽  
Daniel J.D. Sullivan

Abstract Acoustic Micro Imaging (AMI) is an established nondestructive technique for evaluation of electronic packages. Non-destructive evaluation of electronic packages is often a critical first step in the Failure Analysis (FA) process of semiconductor devices [1]. The molding compound to die surface interface of the Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) packages is an important interface to acquire for the FA process. Occasionally, with these packages, the standard acoustic microscopy technique fails to identify defects at the molding compound to die surface interface. The hard to identify defects are found at the edge of the die next to the bond pads or under the bonds wires. This paper will present a technique, Backside Acoustic Micro Imaging (BAMI) analysis, which can better resolve the molding compound to die surface interface at the die edge by sending the acoustic signal through the backside of the PBGA and PQFP packages.


2007 ◽  
Vol 129 (4) ◽  
pp. 382-390 ◽  
Author(s):  
Pradeep Lall ◽  
Nokibul Islam ◽  
John Evans ◽  
Jeff Suhling

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms, which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards (PCBs). Automotive applications typically use high glass-transition temperature laminates such as FR4-06 glass∕epoxy laminate material (Tg=164.9°C). In application environments, metal backing of printed circuit boards is being targeted for thermal dissipation, mechanical stability, and interconnections reliability. In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays on non-metal-backed substrates (Lall et al., 2003, “Model for BGA and CSP in Automotive Underhood Environments,” Electronic Components and Technology Conference, New Orleans, LA, May 27–30, pp. 189–196;Syed, A. R., 1996, “Thermal Fatigue Reliability Enhancement of Plastic Ball Grid Array (PBGA) Packages,” Proceedings of the 1996 Electronic Components and Technology Conference, Orlando, FL, May 28–31, pp. 1211–1216;Evans et al., 1997, “PBGA Reliability for Under-the-Hood Automotive Applications,” Proceedings of InterPACK ’97, Kohala, HI, Jun. 15–19, pp. 215–219;Mawer et al., 1999, “Board-Level Characterization of 1.0 and 1.27mm Pitch PBGA for Automotive Under-Hood Applications,” Proceedings of the 1999 Electronic Components and Technology Conference, San Diego, CA, Jun. 1–4, pp. 118–124) and ceramic ball-grid arrays (BGAs) on non-metal-backed substrates (Darveaux, R., and Banerji, K., 1992, “Constitutive Relations for Tin-Based Solder Joints,” IEEE Trans-CPMT-A, Vol. 15, No. 6, pp. 1013–1024;Darveaux et al., 1995, “Reliability of Plastic Ball Grid Array Assembly,” Ball Grid Array Technology, Lau, J., ed., McGraw-Hill, New York, pp. 379–442;Darveaux, R., 2000, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation,” Proceedings of 50th ECTC, May, pp. 1048–1058). Delamination of PCBs from metal backing has also been investigated. The test vehicle is a metal-backed FR4-06 laminate. The printed circuit board has an aluminum metal backing, attached with pressure sensitive adhesive (PSA). Component architectures tested include plastic ball-grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL. Crack propagation and intermetallic thickness data have been acquired as a function of cycle count. Reliability data have been acquired on all these architectures. Material constitutive behavior of PSA has been measured using uniaxial test samples. The measured constitutive behavior has been incorporated into nonlinear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.


2000 ◽  
Vol 123 (3) ◽  
pp. 232-237 ◽  
Author(s):  
Sarang Shidore ◽  
Tien Yu Tom Lee

A detailed model of a die-up 256-pin Plastic Ball Grid Array (PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, four compact models were derived; two two-resistor models (one created through a two-point computational cold plate test; the other using the DELPHI optimization approach), a multi-resistor Star network model and a shunt network model. The latter three models were derived using the methodology established by the DELPHI (Development of Libraries of Physical models for an Integrated design environment) project. The four compact models and the detailed model were each placed in natural convection and forced convection (velocities of 1,2, and 4 m/s) environments. Good agreement was obtained for the die-junction temperature rise for both the detailed and the shunt compact models. The star and two-resistor models were seen to be inferior in terms of accuracy. The two-resistor model created using the DELPHI methodology was found to be superior compared to the one created with the computational cold-plate test. The star model showed little gain in performance as compared to the DELPHI two-resistor model.


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