A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

26th IEEE VLSI Test Symposium (vts 2008) ◽

10.1109/vts.2008.37 ◽

2008 ◽

Cited By ~ 6

Author(s):

K. Christou ◽

M.K. Michael ◽

P. Bernardi ◽

M. Grosso ◽

E. Sanchez ◽

...

Keyword(s):

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Generation Technique

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Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Cited By ~ 46

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Parallel Pattern

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Cited By ~ 30

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Cited By ~ 15

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Functional-based ATPG for path delay faults

2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390) ◽

10.1109/ssmsd.2000.836465 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Michael ◽

S. Tragoudas

Keyword(s):

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320072 ◽

2006 ◽

Author(s):

Shun-yen Lu ◽

Pei-ying Hsieh ◽

Jing-jia Liou

Keyword(s):

Critical Path ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Linear Structures ◽

Critical Path Delay

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Self-checking synchronous FSM network design for path delay faults

2017 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2017.8110129 ◽

2017 ◽

Cited By ~ 6

Author(s):

S. Ostanin

Keyword(s):

Network Design ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Cited By ~ 30

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785514 ◽

2010 ◽

Cited By ~ 1

Author(s):

Bo Yao ◽

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Transition Path

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Identification of critical primitive path delay faults without any path enumeration

2010 28th VLSI Test Symposium (VTS) ◽

10.1109/vts.2010.5469629 ◽

2010 ◽

Cited By ~ 7

Author(s):

Kyriakos Christou ◽

Maria K. Michael ◽

Stelios Neophytou

Keyword(s):

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Automation and Remote Control ◽

10.1134/s0005117921110102 ◽

2021 ◽

Vol 82 (11) ◽

pp. 1949-1965

Author(s):

A. Yu. Matrosova ◽

S. V. Chernyshov ◽

O. Kh. Kim ◽

E. A. Nikolaeva

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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