Proceedings ETC 93 Third European Test Conference
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Published By IEEE Comput. Soc. Press

0818633603

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New methods for parallel pattern fast fault simulation for synchronous sequential circuits

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246617 ◽

2002 ◽

Author(s):

M. Mojtahedi ◽

W. Geisselhardt

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

New Methods ◽

Synchronous Sequential Circuits ◽

Parallel Pattern

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Cited By ~ 15

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Random test length for bounded faults in RAMs

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246522 ◽

2002 ◽

Cited By ~ 4

Author(s):

R. David ◽

J.A. Brzozowski ◽

H. Jurgensen

Keyword(s):

Test Length ◽

Random Test

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Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246575 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Andrews

Keyword(s):

Ieee 1149.1

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RT level test scheduling

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246599 ◽

2002 ◽

Cited By ~ 5

Author(s):

J. Blatny ◽

Z. Kotasek ◽

J. Hlavicka

Keyword(s):

Test Scheduling

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Incoming inspection of FPGA's

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246578 ◽

2002 ◽

Cited By ~ 27

Author(s):

C. Jordan ◽

W.P. Marnane

Keyword(s):

Incoming Inspection

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Analysis of voltage forcing consequences during in-circuit testing

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246619 ◽

2002 ◽

Author(s):

M. Sartori ◽

A. Chiado Piat ◽

A. Gallesio ◽

C. Truzzi ◽

L. Bonaria

Keyword(s):

Circuit Testing

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Design for testability techniques applicable to analog circuits

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246612 ◽

2002 ◽

Author(s):

J.L. Huertas ◽

A. Rueda ◽

D. Vazquez

Keyword(s):

Analog Circuits ◽

Design For Testability

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A fuzzy decision-making approach for test space exploration

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246535 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Fares ◽

B. Kaminska

Keyword(s):

Decision Making ◽

Space Exploration ◽

Fuzzy Decision Making ◽

Fuzzy Decision ◽

Test Space

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Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246562 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Al-Khalili ◽

M.O. Esonu ◽

C. Rozon

Keyword(s):

Testability Analysis

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Proceedings ETC 93 Third European Test ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

New methods for parallel pattern fast fault simulation for synchronous sequential circuits

Fast test pattern generation for all path delay faults considering various test classes

Random test length for bounded faults in RAMs

Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

RT level test scheduling

Incoming inspection of FPGA's

Analysis of voltage forcing consequences during in-circuit testing

Design for testability techniques applicable to analog circuits

A fuzzy decision-making approach for test space exploration

Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

Proceedings ETC 93 Third European Test Conference
Latest Publications