An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance

Abstract Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.

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Evaluation of the Resistance of Individual Si Die to Cracking

10.31399/asm.cp.istfa1998p0197 ◽

1998 ◽

Author(s):

R. Berriche ◽

R.K. Lowry ◽

M.I. Rosenfield

Keyword(s):

Thermal Cycling ◽

Hardness Test ◽

Mechanical Stresses ◽

Test Method ◽

Processing Conditions ◽

Micro Hardness ◽

Test Methodology ◽

Vickers Micro Hardness

Abstract The present work investigated the use of the Vickers micro-hardness test method to determine the resistance of individual die to cracking. The results are used as an indicator of resistance to failure under the thermal and mechanical stresses of packaging and subsequent thermal cycling. Indentation measurements on die back surfaces are used to determine how changes in wafer backside processing conditions affect cracks that form around impressions produced at different loads. Test methodology and results obtained at different processing conditions are discussed.

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Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0407 ◽

2006 ◽

Author(s):

Ray Talacka ◽

Nandu Tendolkar ◽

Cynthia Paquette

Keyword(s):

High Performance ◽

Yield Enhancement ◽

Test Time ◽

Balance Test ◽

Specific Test ◽

Defect Location ◽

Test Methodology ◽

Memory Arrays ◽

Scan Chain ◽

Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

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Application of the Depth-of-Penetration Test Methodology to Characterize Ceramics for Personnel Protection

10.21236/ada376698 ◽

2000 ◽

Cited By ~ 6

Author(s):

Thomas J. Moynihan ◽

Shun-Chin Chou ◽

Audreyk L. Mihalcin

Keyword(s):

Penetration Test ◽

Depth Of Penetration ◽

Test Methodology

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Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽

10.3390/electronics10131572 ◽

2021 ◽

Vol 10 (13) ◽

pp. 1572

Author(s):

Ehab A. Hamed ◽

Inhee Lee

Keyword(s):

Soft Error ◽

Error Tolerance ◽

Cmos Process ◽

Flip Flop ◽

Single Event Upsets ◽

Area Overhead ◽

Fair Comparison ◽

Reference Design ◽

Radiation Hardened ◽

Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

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