Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2006.888268 ◽

2007 ◽

Vol 26 (7) ◽

pp. 1339-1345 ◽

Cited By ~ 2

Author(s):

Loganathan Lingappan ◽

Niraj K. Jha

Keyword(s):

Design For Testability ◽

Register Transfer Level ◽

Efficient Design ◽

Register Transfer

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A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2008.927757 ◽

2008 ◽

Vol 27 (9) ◽

pp. 1535-1544 ◽

Cited By ~ 14

Author(s):

Hideo Fujiwara ◽

Hiroyuki Iwata ◽

Tomokazu Yoneda ◽

Chia Yee Ooi

Keyword(s):

Design For Testability ◽

Register Transfer Level ◽

Register Transfer ◽

Time Expansion

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A design-for-testability technique for register-transfer level circuits using control/data flow extraction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.712102 ◽

1998 ◽

Vol 17 (8) ◽

pp. 706-723 ◽

Cited By ~ 34

Author(s):

I. Ghosh ◽

A. Raghunathan ◽

N.K. Jha

Keyword(s):

Data Flow ◽

Design For Testability ◽

Register Transfer Level ◽

Control Data ◽

Register Transfer

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Design for testability using register-transfer level partial scan selection

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486225 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Motohara ◽

S. Takeoka ◽

T. Hosokawa ◽

M. Ohta ◽

Y. Takai ◽

...

Keyword(s):

Design For Testability ◽

Register Transfer Level ◽

Partial Scan ◽

Register Transfer ◽

Partial Scan Selection

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Design for testability using register-transfer level partial scan selection

Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95 ◽

10.1145/224818.224900 ◽

1995 ◽

Author(s):

Akira Motohara ◽

Sadami Takeoka ◽

Toshinori Hosokawa ◽

Mitsuyasu Ohta ◽

Yuji Takai ◽

...

Keyword(s):

Design For Testability ◽

Register Transfer Level ◽

Partial Scan ◽

Register Transfer ◽

Partial Scan Selection

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2406 ◽

2011 ◽

Vol 2 (4) ◽

pp. 61-68

Author(s):

M S Suma

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Sequential Circuits ◽

Register Transfer ◽

Combinational And Sequential Circuits

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Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Cited By ~ 12

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Dft Method ◽

Register Transfer Level ◽

Register Transfer

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Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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