scholarly journals STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

VLSI Design ◽  
1994 ◽  
Vol 1 (4) ◽  
pp. 327-334
Author(s):  
Rochit Rajsuman ◽  
Kamal Rajkanan
Keyword(s):  
Fault Diagnosis ◽  
Design Method ◽  
Random Access ◽  
Standard Test ◽  
Test Time ◽  
Design Time ◽  
Memory Address ◽  
Hardware Overhead ◽  
Test Algorithm ◽  
Time Required

We present a design method (called STD architecture) to design large memories so that the test time does not increase with the increasing size of memory. Large memories can be constructed by using several small blocks of memory. The memory address decoder is divided into two or more levels and designed such that during the test mode all small memory blocks are accessed together. With the help of modified decoder, all small memory blocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory is equal to the time required to test one small block. The proposed design is highly structured and hardware overhead is negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method a constant test time can be achieved irrespective of the memory size. STD architecture is applicable to memory chips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis.

scholarly journals Designing Multi-Agent System Organisations for Flexible Runtime Behaviour

2020 ◽  
Vol 10 (15) ◽  
pp. 5335
Author(s):  
Kathleen Keogh ◽  
Liz Sonenberg
Keyword(s):  
Design Method ◽  
Multi Agent System ◽  
Improve Performance ◽  
Uncertain Environments ◽  
Agent System ◽  
Meta Model ◽  
Design Time ◽  
Organisational Support ◽  
Multi Agent ◽  
Associated Design

We address the challenge of multi-agent system (MAS) design for organisations of agents acting in dynamic and uncertain environments where runtime flexibility is required to enable improvisation through sharing knowledge and adapting behaviour. We identify behavioural features that correspond to runtime improvisation by agents in a MAS organisation and from this analysis describe the OJAzzIC meta-model and an associated design method. We present results from simulation scenarios, varying both problem complexity and the level of organisational support provided in the design, to show that increasing design time guidance in the organisation specification can enable runtime flexibility afforded to agents and improve performance. Hence the results demonstrate the usefulness of the constructs captured in the OJAzzIC meta-model.

A New Design Method for the Fault Diagnosis on the Rotating Rectifier of Aeronautic Synchronous Generator

2012 ◽  
Vol 548 ◽  
pp. 544-547
Author(s):  
Yong Zhi Liu ◽  
Cong Liu
Keyword(s):  
Fault Diagnosis ◽  
Feature Vector ◽  
Design Method ◽  
Synchronous Generator ◽  
New Method ◽  
Test Analysis ◽  
Exciting Current ◽  
On Line

A new method of fault diagnosis on the rotating rectifier of aeronautic synchronous is raised in the work. Firstly, the condition, truth and approach of EMD are introduced, and the method and steps of building up the feature vector are also included, Secondly the theories of LS-SVM and the arithmetic in the classification are also included. Finally taking the faults of one and two diodes turning off for example, after extracting the feature vector of exciting current based on EMD and establishing the classifying method based on Gauss RBF LS-SVM, the test, analysis and comparison can be on between LS-SVM and NN the conclusion can be got that the classified method referred in the work owns higher exactness, takes less time and has more application on the on-line fault diagnosis NN.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals IPG as a new method to improve the agility of the initial analysis of the inventive design

2021 ◽  
Vol 49 (3) ◽  
pp. 549-562
Author(s):  
Masih Hanifi ◽  
Hicham Chibane ◽  
Rémy Houssin ◽  
Denis Cavallucci
Keyword(s):  
Inverse Problem ◽  
Design Method ◽  
New Method ◽  
Significant Progress ◽  
Initial Analysis ◽  
The Subject ◽  
Time Required

TRIZ method has long proven its value without appearing to the industrial world as inevitable. Design researchers have therefore addressed the limitations of the TRIZ method and have overcome them with more systematic approaches. Among these, the Inventive Design Method (IDM) has been the subject of several articles and put into practice in the industry. It is considered an improvement over TRIZ but still suffers from some drawbacks in terms of the time-consuming nature of its implementation. We focused on the IDM process by trying to both identify its areas of inefficiencies while attempting to preserve the quality of its deliverables. Our approach consists of applying the precepts of Lean to IDM. The result is the Inverse Problem Graph (IPG) method, inspired by IDM, but offering significant progress in reducing the time required to mobilize experts while preserving its inventive outcomes. This article outlines our approach for the construction of this new method.

scholarly journals Critical appraisal of speech in noise tests: a systematic review and survey

2016 ◽  
Vol 5 (1) ◽  
pp. 13 ◽  
Author(s):  
Suhani Sharma ◽  
Rajesh Tripathy ◽  
Udit Saxena
Keyword(s):  
Critical Appraisal ◽  
Measurement Model ◽  
Test Time ◽  
Hearing Research ◽  
Speech In Noise ◽  
Hearing In Noise ◽  
Instrument Bias ◽  
Noise Test ◽  
Time Required ◽  
Selection Of

Speech in noise tests that measure the perception of speech in presence of noise are now an important part of audiologic tests battery and hearing research as well. There are various tests available to estimate the perception of speech in presence of noise, for example, connected sentence test, hearing in noise test, words in noise, quick speech-in-noise test, bamford-kowal-bench speech-in-noise test, and listening in spatialized noise-sentences. All these tests are different in terms of target age, measure, procedure, speech material, noise, normative, etc. Because of the variety of tests available to estimate speech-in-noise abilities, audiologists often select tests based on their availability, ease to administer the test, time required in running the test, age of the patient, hearing status, type of hearing disorder and type of amplification device if using. A critical appraisal of these speech-in-noise tests is required for the evidence based selection and to be used in audiology clinics. In this article speech-in-noise tests were critically appraised for their conceptual model, measurement model, normatives, reliability, validity, responsiveness, item/instrument bias, respondent burden and administrative burden. Selection of a standard speech-in-noise test based on this critical appraisal will also allow an easy comparison of speech-in-noise ability of any hearing impaired individual or group across audiology clinics and research centers. This article also describes the survey which was done to grade the speech in noise tests on the various appraisal characteristics.

scholarly journals Intrinsic Run-time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security

2018 ◽  
Author(s):  
Nikolaos Athanasios Anagnostopoulos ◽  
Tolga Arul ◽  
Yufan Fan ◽  
Christian Hatzfeld ◽  
André Schaller ◽  
...  
Keyword(s):  
Random Access ◽  
Physical Unclonable Functions ◽  
Generation Times ◽  
Speed Up ◽  
Run Time ◽  
Commercial Off The Shelf ◽  
Cost Efficient ◽  
Statistical Relationships ◽  
The Times ◽  
Time Required

Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demonstrated, the times needed in order to generate their responses may prohibit their widespread usage. In order to address this issue, the Row Hammer PUF has been proposed by Schaller et al. [1], which leverages the row hammer effect in DRAM modules to reduce the retention times of their cells and, therefore, significantly speed up the generation times for the responses of PUFs based on these retention times. In this work, we extend the work of Schaller et al. by presenting a run-time accessible implementation of this PUF and further reducing the time required for the generation of its responses. Additionally, we also provide a more thorough investigation of the effects of temperature variations on the the Row Hammer PUF and briefly discuss potential statistical relationships between the cells used to implement it. As our results prove, the Row Hammer PUF could potentially provide an adequate level of security for Commercial Off-The-Shelf (COTS) devices, if its dependency on temperature is mitigated, and, may therefore, be commercially adopted in the near future.

scholarly journals A Durable Hybrid RAM Disk with a Rapid Resilience for Sustainable IoT Devices

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2159 ◽  
Author(s):  
Sung Hoon Baek ◽  
Ki-Woong Park
Keyword(s):  
Storage System ◽  
Random Access ◽  
Solid State Drive ◽  
Storage Devices ◽  
Disk Storage ◽  
Block Level ◽  
Iot Platforms ◽  
Iot Devices ◽  
Time Required ◽  
Time Critical

Flash-based storage is considered to be a de facto storage module for sustainable Internet of things (IoT) platforms under a harsh environment due to its relatively fast speed and operational stability compared to disk storage. Although their performance is considerably faster than disk-based mechanical storage devices, the read and write latency still could not catch up with that of Random-access memory (RAM). Therefore, RAM could be used as storage devices or systems for time-critical IoT applications. Despite such advantages of RAM, a RAM-based storage system has limitations in its use for sustainable IoT devices due to its nature of volatile storage. As a remedy to this problem, this paper presents a durable hybrid RAM disk enhanced with a new read interface. The proposed durable hybrid RAM disk is designed for sustainable IoT devices that require not only high read/write performance but also data durability. It includes two performance improvement schemes: rapid resilience with a fast initialization and direct byte read (DBR). The rapid resilience with a fast initialization shortens the long booting time required to initialize the durable hybrid RAM disk. The new read interface, DBR, enables the durable hybrid RAM disk to bypass the disk cache, which is an overhead in RAM-based storages. DBR performs byte–range I/O, whereas direct I/O requires block-range I/O; therefore, it provides a more efficient interface than direct I/O. The presented schemes and device were implemented in the Linux kernel. Experimental evaluations were performed using various benchmarks at the block level till the file level. In workloads where reads and writes were mixed, the durable hybrid RAM disk showed 15 times better performance than that of Solid-state drive (SSD) itself.

scholarly journals Impact of Energy Dependence on Ground Level and Avionic SEE Rate Prediction When Applying Standard Test Procedures

Aerospace ◽  
2019 ◽  
Vol 6 (11) ◽  
pp. 119
Author(s):  
Matteo Cecchetto ◽  
Rubén García Alía ◽  
Frédéric Wrobel
Keyword(s):  
Cross Sections ◽  
Random Access ◽  
Ground Level ◽  
High Energy ◽  
Standard Test ◽  
Fissile Material ◽  
Test Procedures ◽  
Relative Contribution ◽  
Standard Procedures ◽  
Commercial Flight

Single event effects (SEEs) in ground level and avionic applications are mainly induced by neutrons and protons, of which the relative contribution of the latter is larger with increasing altitude. Currently, there are two main applicable standards—JEDEC JESD89A for ground level and IEC 62396 for avionics—that address the procedure for testing and qualifying electronics for these environments. In this work, we extracted terrestrial spectra at different altitudes from simulations and compared them with data available from the standards. Second, we computed the SEE rate using different approaches for three static random access memory (SRAM) types, which present a strong SEE response dependence with energy. Due to the presence of tungsten, a fissile material when interacting with high energy hadrons, the neutron and proton SEE cross sections do not saturate after 200 MeV, but still increase up to several GeV. For these memories, we found standard procedures could underestimate the SEE rate by a factor of up to 4-even in ground level applications—and up to 12 times at 12 km. Moreover, for such memories, the contribution from high energy protons is able to play a significant role, comparable to that of neutrons, even at commercial flight altitudes, and greater at higher altitudes.

EMEDS: A System to Determine Ejection Layout for Rapid-Tooled Injection Molds

2003 ◽  
Author(s):  
Sundiata K. Jangha ◽  
David W. Rosen
Keyword(s):  
Mold Design ◽  
Design Synthesis ◽  
Design Time ◽  
Solution Algorithms ◽  
Molded Part ◽  
Ejection Force ◽  
Mold Fabrication ◽  
Ejection Mechanism ◽  
Problem Formulations ◽  
Time Required

One of the main issues in injection molding is the amount of time required to design and fabricate a mold once a part representation has been created. Rapid tooling methods, the usage of rapid prototyping methods to fabricate molds, have been developed to speed up mold fabrication, but mold design time remains a bottleneck. The design of ejection mechanisms for rapid tools is investigated in this paper. By eliminating elements from a mold that are specific to the molded part, mold design time can be reduced. For instance, the use of a standardized ejector plate with an array of pre-drilled holes significantly reduces part specific elements from the ejector mechanism. The EMEDS system, Ejection Mechanism Design Synthesis, was developed to facilitate the rapid design and incorporation of ejection into rapid tools with standardized ejector plates. Problem formulations and solution algorithms will be presented for the two main elements of EMEDS, the Pin Composer and Pin Locator. In support of EMEDS, an analytical model of ejection force was developed and will be presented here. Application of the EMEDS system to an example illustrates the design of an ejection mechanism for an industrial part.

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