Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation

2002 ◽  
Author(s):  
Z. Jaworski ◽  
M. Niewczas ◽  
W. Kuzmicz
Keyword(s):  
Analog Circuits ◽  
Test Generation ◽  
Fault Analysis ◽  
Parametric Faults ◽  
Inductive Fault Analysis

scholarly journals Phase difference analysis technique for parametric faults BIST in CMOS analog circuits

2018 ◽  
Vol 15 (9) ◽  
pp. 20180175-20180175 ◽  
Author(s):  
Chatchai Wannaboon ◽  
Nattagit Jiteurtragool ◽  
Wimol San-Um ◽  
Masayoshi Tachibana
Keyword(s):  
Phase Difference ◽  
Analog Circuits ◽  
Difference Analysis ◽  
Parametric Faults ◽  
Analysis Technique ◽  
Cmos Analog Circuits

Optimization-based multifrequency test generation for analog circuits

1996 ◽  
Vol 9 (1-2) ◽  
pp. 59-73 ◽  
Author(s):  
A. Abderrahman ◽  
B. Kaminska ◽  
E. Cerny
Keyword(s):  
Analog Circuits ◽  
Test Generation

scholarly journals Test Generation Algorithm for Fault Detection of Analog Circuits Based on Extreme Learning Machine

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Jingyu Zhou ◽  
Shulin Tian ◽  
Chenglin Yang ◽  
Xuelong Ren
Keyword(s):  
Extreme Learning Machine ◽  
Analog Circuits ◽  
Test Generation ◽  
Cost Effective ◽  
Fault Classification ◽  
The Novel ◽  
Analog Device ◽  
Generation Algorithm ◽  
New Process ◽  
Learning Machine

This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments.

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